Apparatus and method for high-level synthesis of a logic circuit

A logic synthesis apparatus comprising:

• a) an input processing unit having means for generating a control description graph according to a behavioral description graph written in a behavioral description language, means for sorting the control description graph according to control conditions and extracting single flows including at least one of partial graphs and closed loops from the sorted control description graph, and means for providing an initial circuit;
• b) a CPU connected to said input processing unit, having means for dividing the single flows into execution steps, means for allocating hardware parts that are necessary to the initial circuit for each of the execution steps and adding an additional hardware part for a circuit part not included in the initial circuit if an optimum combination of the hardware parts is not found, means for converting each of the single flows into a corresponding finite state machine and combining the finite state machines into one finite state machine, first storage means for storing synthesis circuit files, and second storage means for storing logic synthesis simplification rules;
• and
• c) an output processing unit connected to said CPU.

A method of logic synthesis comprising the steps of:

• a) generating a control description graph according to a behavioral description graph written in a behavioral description language;
• b) sorting the control description graph according to control conditions and extracting single flows including at least one of partial graphs and closed loops from the sorted control description graph;
• c) providing an initial circuit;
• and
• d) modifying the initial circuit by adding an additional circuit part not included in the initial circuit to obtain a required logic circuit.