Display control apparatus
AssigneeCanon Kabushiki Kaisha
InventorsTakashi Tsunoda, Hideo Kanno
Life of this patent
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Abstract
In a video display control, a phase locked loop (PLL) circuit generates a multiplied frequency signal from a reference signal. The stability of the PLL circuit is maintained even when the reference signal has different frequencies by providing a number of multiplication values corresponding to the number of different reference signal frequencies and switching the multiplication value when a change in frequency is detected to stabilize the PLL circuit.
Claims8
A display control apparatus for generating a dot clock signal to display a video signal in response to a synchronous signal, said display control apparatus comprising:
- comparison means for comparing a synchronous signal with a divided signal;
- clock generation means for generating a dot clock signal for display according to results obtained by said comparison means;
- storage means for storing first and second values for alteration of said dot clock signal for display;
- divider means for generating said divided signal responsive to said stored values and said dot clock signal for display;
- and
- selection means for selecting the first or second value stored in said storage means in accordance with a change in the synchronous signal.
A display control method for generating a dot clock signal in response to a synchronous signal to control a video display, comprising the steps of:
- comparing the synchronous signal with a divided signal;
- generating a dot clock signal for display responsive to a result of said comparison;
- storing first and second values for alteration of the dot clock signal;
- generating the divided signal responsive to the stored values and the dot clock signal;
- and
- selecting the stored first or second value in response to a change in the synchronous signal.
An information processing apparatus comprising:
- receiving means for receiving an image signal and a synchronous signal which are provided from outside;
- comparison means for comparing the synchronous signal with a divided signal;
- clock generation means for generating a dot clock signal for display according to results obtained by said comparison means;
- storage means for storing first and second values for alteration of said dot clock signal for display;
- divider means for generating said divided signal responsive to said stored values and said dot clock signal for display;
- selection means for selecting the first or second value stored in said storage means in accordance with a change in the synchronous signal;
- sampling means for sampling said image signal based on said dot clock signal;
- and
- display control means for displaying an image signal sampled by said sampling means on a display device.
Dependencies are inferred from the claim text.