Graphic processing apparatus and method

A graphic processing apparatus comprising:

• a processor for executing an operation process;
• a display for displaying pixel data;
• a memory for storing, in an integrated manner, at least a program for executing an operation process by said processor and a plurality of said pixel data, said memory including a pair of display buffers each for holding at least a raster portion of said pixel data,
• a memory data supplier for supplying said current pixel data alternately stored in one of said first and second display buffer of said memory to said display;
• and
• a compare means for comparing a time required to write a remaining said next pixel data in one of said first and second display buffer with a remaining operation time to output a remaining said current pixel data from an opposite one of said first and second display buffer to said display means for providing control of priority accessing to said memory for said pixel data, so as to prioritize an access of said pixel data from said memory over a program access of said program from said memory when a time required to write a remaining said next pixel data approaches said remaining operation time required to output said current pixel data.

A graphic processing apparatus comprising:

• a rendering processor for controlling generation of graphic data;
• a dynamic memory for storing, in an integrated manner, both program data and pixel data generated by said rendering processor;
• a display unit including a pair of display buffers for displaying content thereof to output pixel data for at least a raster stored in said dynamic memory to a display, wherein, for subsequent display cycles, one of a first display buffer and a second display buffer of said pair of display buffers is used as a write buffer for writing a next pixel data thereto, while an opposite one of said first display buffer and said second display buffer is used as a read buffer for reading a current pixel data therefrom to said display;
• and,
• a control means connected with said display unit for comparing a time required to write a next pixel data remaining in said dynamic memory to said write buffer with a remaining operation time required to display a current pixel data remaining in said read buffer;
• whereby a row address is designated to said dynamic memory and data in different column addresses within said designated row address are successively accessed, and a number of times of successive column accesses is varied in accordance with a result of a comparison made in said control means to assure an integrity of a display of said pixel data on said display by prioritizing accessing of said pixel data from said dynamic memory over said program data when a time required to write a remaining said next pixel data approaches said remaining operation time to display said current pixel data.