Display data readout circuit

A display data read out circuit for reading out display data from an external memory composed of an SRAM, comprising:

• a CPU designed for fetching and decoding an instruction in a M1 cycle including a first half period and a second half period, the second half period of said M1 cycle being allotted to a refresh cycle;
• data and address buses for exchanging data between said CPU and said external memory;
• a display data address circuit for generating display data addresses;
• and
• an address switching circuit connected with said display data address circuit and said CPU, said address switching circuit outputting a display data address from said display data address circuit into said external memory via an address bus when a refresh signal from said CPU is in an enable state during the second half period of said M1 cycle, and said address switching circuit outputting an address from said CPU into said external memory via said address bus when said refresh signal from said CPU is not in said enable state.