Amendable static random access memory

An amendable static random access memory, which can be modified to a reduced static random access memory when a portion of the original amendable static random access memory is corrupt, said amendable static random access memory divided into a plurality of memory blocks for storing data and each memory block divided into a plurality of memory sections, said amendable static random access memory further comprising:

• a plurality of local sense amplifiers for amplifying data from the static random access memory, wherein each memory section comprises the same number of said local sense amplifiers and said local sense amplifiers in each memory section are divided into normal and amending ones;
• a plurality of common sense amplifiers for amplifying data from said plurality of local sense amplifiers, wherein each memory block comprises the same number of said common sense amplifiers and said common sense amplifiers in each memory block are divided into normal and amending common sense amplifiers, as well as that each of the normal common sense amplifiers in that memory block receives data from a corresponding one of the normal local sense amplifiers in each of the memory sections of that memory block and each amending common sense amplifier in that memory block receives data coming from a corresponding amending local sense amplifier in a corresponding memory section of that memory block;
• a plurality of I/O buffers for buffering the data from said plurality of common sense amplifiers, wherein each memory block comprises the same number of said I/O buffers and said I/O buffers in each memory block are divided into normal and amending I/O buffers, as well as that each of the normal I/O buffers in said memory block receives data coming from a corresponding one of the common sense amplifiers in that same memory block;
• and
• a plurality of switching circuits for switching a plurality of interconnections between said plurality of amending common sense amplifiers and said plurality of I/O buffers, wherein each of said plurality of switching circuits is coupled through its input terminal to a corresponding one of the amending common sense amplifiers in that memory block and through its output terminals to each of said normal I/O buffers in that memory block.