Synthesizable architecture for all-digital minimal jitter frequency synthesizer

A frequency synthesizing circuit for the generation of periodic output frequency periods having a first level and a second level, wherein said selected signal periods constitute a number of at least two periods of a periodic input reference frequency, comprising:

• a) a count series retention table to retain a series of counting integers representing the number of periods of said periodic input reference frequency, wherein said counting integers are generated in a count compiler and wherein said count compiler forms said counting integers by a method comprising the steps of:
• dividing of one of the selected periods by the period of the periodic input reference frequency to form a quotient,
• decomposing of the quotient into a weighted average of a first integer and a second integer such that the first integer is a largest integer lesser than the quotient and the second integer is a value of the first integer plus one,
• simplifying said quotient to a mixed number having an integer and a fraction, wherein the fraction has a numerator and a denominator, and
• creating the series of counting integers that include the first and second integers, wherein a first quantity of counting integers is the value of the denominator and a second quantity of second integers in the series of integers is the value of a residue of a dividing of the numerator by the denominator and wherein the first and second integers are disbursed in a uniform manner within the series of counting integers,
• wherein a plurality of the series of counting integers are placed in said count series retention table by the count compiler, wherein each series of counting integers represent one of the selected signal periods, and wherein a count select signal chooses one of the series of counting integers and the count select signal sequentially places each counting integer of the series of counting integers on a count output;
• b) a count incrementing means coupled to the count series retention table to increment a count signal having a count select decoder coupled to the count select signal to determine the number of counting integers to be transferred from said count series retention table, and an output counter coupled to the periodic output frequency to increment the count signal to a next integer in the series of counting integers;
• and
• c) a frequency generation means coupled to the count retention table and the count incrementing means to develop the periodic output frequency, including:
• a periodic input reference frequency counter coupled to the periodic input reference frequency and to the count output, wherein said periodic input reference frequency counter will create a max count signal when the number of periods of the periodic input reference frequency is equal to the counting integer, and
• a toggling means coupled to the periodic input reference frequency counter to alternate the periodic output frequency from the first level to the second level and return to the first level at the reception of each counting signal.