Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors

A programmable logic array integrated circuit device comprising:

• a plurality of logic regions, each of which has a plurality of input terminals and at least one output terminal, and each of which is programmable to produce at its output terminal an output logic signal which is any of a plurality of logic functions of input logic signals applied to its input terminals, said logic regions being grouped in a plurality of blocks of said logic regions such that each of said blocks includes a respective subplurality of adjacent ones of said logic regions, said blocks being disposed on said integrated circuit in a two-dimensional array of intersecting rows and columns of said blocks, each of said rows being subdivided into a plurality of sub-rows of said blocks such that each of said sub-rows includes a respective subplurality of adjacent ones of said blocks in the row of which that sub-row is a part;
• a plurality of sub-row conductors associated with each of said sub-rows, each of said sub-row conductors extending along the length of the associated sub-row;
• a plurality of column conductors associated with each of said columns, each of said column conductors extending along the length of the associated column;
• a plurality of block feeding conductors associated with each of said blocks, each of said block feeding conductors extending along the logic regions of the associated block;
• a first programmable switch array associated with each of said pluralities of block feeding conductors for selectively connecting said block feeding conductors to sub-row conductors associated with the sub-row which includes the block associated with said block feeding conductors;
• a second programmable switch array associated with each of said logic regions for selectively connecting the input terminals of said logic region to block feeding conductors associated with the block which includes said logic region;
• a third programmable switch array associated with each of said logic regions for selectively applying the logic output signal of said logic region to sub-row and column conductors respectively associated with the sub-row and column which include the block that includes said logic region;
• and
• a fourth programmable switch array associated with each adjacent pair of sub-rows in each row for selectively connecting sub-row conductors associated with one of the associated pair of sub-rows to sub-row conductors associated with the other of the associated pair of sub-rows.