Analog autonomous test bus framework for testing integrated circuits on a printed circuit board

A system for routing data related to a test of a core circuit of an integrated circuit chip, which core circuit is at least partly analog and has an input and an output, the system comprising:

• (a) a first test bus external to the integrated circuit,
• (b) a source of control signals,
• (c) a first switching cell, said first switching cell having a first input, control second input, an output, and a bidirectional test port,
• (d) first means for coupling the switching cell second input with the source of control signals,
• (e) second means for coupling the switching cell input with an output of the core circuit,
• (f) third means for coupling the switching cell test port with the first test bus,
• (g) fourth means for coupling the switching cell output to a normal output path for the core circuit, and
• (h) said first switching cell in response to signals received at its second input being placeable into one of plural states including a first state, a second state, and a third state, when placed in its first state said first switching cell coupling its first input with its output to form a normal path from the core circuit, when placed in its second state said first switching cell coupling its test port with its output to form a test output path, when placed in its third state said first switching cell coupling its first input with its test port to form a test output path for the core circuit.

A carrier comprising

• a. a plurality of integrated circuit chips, each comprising a core circuit to be tested, at least one of the core circuits being at least partly analog;
• b. first and second test buses, external to the integrated circuit chips;
• c. a source of control signals;
• d. a plurality of switching cells, each switching cell comprising a first input, control second input, an output, and a bidirectional test port, the switching cells being arranged in a boundary scan like chain around the integrated circuit chips, each switching cell being either an input switching cell or an output switching cell
• I. each input switching cell being disposed to route test data related to at least a respective input function of a respective core circuit of a respective one of the integrated circuits, such respective input switching cell, in response to signals received at its second input being placeable into one of plural states including a first state, a second state, and a third state,
• .alpha.. when placed in its first state, such respective input switching cell coupling its first input with its output to form a normal path to the respective core circuit of that input switching cell,
• .beta.. when placed in its second state, such respective input switching cell coupling its test port with its output to form a test input path for the respective core circuit of that input switching cell, and
• .gamma.. when placed in its third state, such respective input switching cell coupling its first input with its test port to form a test output path;
• and
• ii. each output switching cell being disposed to route test data related to at least a respective output function of a respective core circuit of a respective one of the integrated circuits, such respective output switching cell, in response to signals received at its second input being placeable into one of plural states including a first state, a second state, and a third state,
• .alpha.. when placed in its first state, such respective output switching cell coupling its first input with its output to form a normal path from the respective core circuit of that output switching cell,
• .beta.. when placed in its second state, such respective output switching cell coupling its test port with its output to form a test input path, and
• .gamma.. when placed in its third state, such respective output switching cell coupling its first input with its test port to form a test output path for the respective core circuit of that output switching cell;
• e. for each respective input switching cell,
• I. respective first means for coupling the respective input switching cell second input with the source of control signals;
• ii. respective second means for coupling the respective input switching cell output with the respective core circuit input;
• iii. respective third means for coupling the respective input switching cell test port with the first test bus;
• and
• iv. respective fourth means for coupling the respective input switching cell input to a normal input path for the core circuit;
• and
• f. for each respective output switching cell,
• I. respective fifth means for coupling the switching cell second input with the source of control signals;
• ii. respective sixth means for coupling the switching cell first input with the output of the core circuit;
• iii. respective seventh means for coupling the test port with the second test bus;
• and
• iv. respective eighth means for coupling the switching cell output with a normal output path of the respective core circuit;
• and
• g. at least one glue circuit or wire coupling the chips via at least one of the input and/or output switching cells.