Low noise 3V/5V CMOS bias circuit
AssigneeCypress Semiconductor Corporation
InventorPing Xu
Life of this patent
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Abstract
The present invention concerns a circuit for implementing a low noise bias circuit that operates at 3 volts, 5 volts or any desired power supply voltage while avoiding production reconfiguration or post-production configuration. The present invention is implemented by using a current source designed to provide a constant current under differing conditions (e.g., such as a variation in temperature, a variation in power supply, or conditions encountered in a fast transistor process). The present circuit provides a means to adapt to varying conditions. The present circuit generally provides two bias signals that are typically used in a pre-driver circuit implementing NMOS and PMOS transistors.
Claims15
A circuit comprising:
- a first circuit configured to generate independent first and second outputs each having a substantially constant current in response to an input voltage;
- a second circuit configured to generate a third output in response to said first and said second outputs, wherein said third output has an increased gain relative to said first and second outputs;
- a third circuit configured to generate a first bias output in response to said third output;
- and
- a fourth circuit configured to generate a second bias output in response to said first bias output, wherein said first and second bias outputs are substantially linear over an input voltage range of from 2.5 to 7.0 volts.
A circuit comprising:
- means for generating independent first and second outputs each having a substantially constant current in response to an input voltage;
- means for generating a third output in response to said first and said second outputs, wherein said third output has an increased gain relative to said first and second outputs;
- means for generating a first bias output in response to said third output;
- and
- means for generating a second bias output in response to said first bias output, wherein said first and second bias outputs are substantially linear when said input voltage ranges from 2.5 to 7.0 volts.
Dependencies are inferred from the claim text.