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US 5,705,827 AGranted
Tunnel transistor and method of manufacturing same
AssigneeNEC Corporation
InventorsToshio Baba, Tetsuya Uemura
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AssigneeNEC Corporation
InventorsToshio Baba, Tetsuya Uemura
Estimating the term…
The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction type to that of the first semiconductor are connected on a substrate or a laminated layer structure comprising a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor of the reverse conduction type to that of the first semiconductor all laminated on a part of a substrate. The tunnel transistor further includes a fourth semiconductor layer formed on an exposed surface of the second semiconductor, having a forbidden band wider than that of the second semiconductor and containing an ionized impurity therein, a gate electrode formed on the fourth semiconductor layer, and a pair of electrodes individually forming ohmic junctions to the first and third semiconductors. Due to the construction, even when the gate voltage is 0, electrons or positive holes are induced in the surface of the second semiconductor, and a tunnel current can be flowed between the source and the drain. Since control of the tunnel current can then be preformed by applying a reverse bias voltage between the gate and the drain, the leak current of the gate can be suppressed.
A tunnel transistor, comprising a junction structure formed on a substrate having a surface disposed in a plane, comprising a non-degenerated second semiconductor disposed on said surface, a degenerated first semiconductor of one conduction type formed at one part of said non-degenerated second semiconductor and a degenerated third semiconductor of a reverse conduction type to that of said first semiconductor at another part of said non-degenerated second semiconductor, said first, second and third semiconductors being connected in a direction parallel to said plane;
In a tunnel transistor, comprising a laminated layer structure which comprises a degenerated first semiconductor of one conduction type formed on a substrate, a non-degenerated second semiconductor overlying said first semiconductor and a degenerated third semiconductor of a reverse conduction type to that of said first semiconductor, said third semiconductor overlying said second semiconductor, a portion of said second and third semiconductors being formed in the shape of a mesa;
A tunnel transistor, comprising a junction structure formed on a substrate having a surface disposed in a plane, comprising a non-degenerated second semiconductor disposed on said surface, a degenerated first semiconductor of one conduction type formed at one part of said non-degenerated second semiconductor and a degenerated third semiconductor of a reverse conduction type to that of said first semiconductor at another part of said non-degenerated second semiconductor, said first, second and third semiconductors being connected in a direction parallel to said plane;
A tunnel transistor, comprising a junction structure formed on a substrate having a surface disposed in a plane, comprising a non-degenerated second semiconductor disposed on said surface, a degenerated first semiconductor of a negative conduction type formed at one part of said non-degenerated second semiconductor and a degenerated third semiconductor of a positive conduction type at another part of said non-degenerated second semiconductor, said first, second and third semiconductors being connected in a direction parallel to said plane;
Dependencies are inferred from the claim text.