Methods of fabricating integrated circuit field effect transistors having reduced-area device isolation regions

A method of fabricating an integrated circuit field effect transistor, the method comprising the steps of:

• forming a pair of spaced apart insulation-filled trench regions in a semiconductor substrate at a surface of the substrate;
• forming an insulated gate on the substrate between and separated from the insulation-filled trench regions, wherein said step of forming an insulated gate comprises the steps of:
• forming a first insulation layer on the substrate between the insulation-filled trench regions;
• forming a conductive layer on the first insulation layer;
• forming a second insulation layer on the conductive layer;
• removing portions of the second insulation layer and the conductive layer to form a gate protector, formed from the second insulation layer, overlying a gate electrode formed from the conductive layer and laterally separated from the insulation-filled trench regions by exposed portions of the first insulation layer;
• implanting ions into portions of the semiconductor substrate underlying the exposed portions of the first insulation layer to form a pair of lightly-doped impurity regions, a respective one of which is laterally disposed between a channel region and a respective one of the insulation-filled trench regions, underlying the gate electrode;
• forming a masking layer on the substrate;
• anisotropically removing portions of the masking layer to expose the gate protector and portions of the first insulation layer laterally disposed between the gate electrode and the insulation-filled trench regions and leave masking regions disposed adjacent sidewall portions of the gate electrode and the gate protector;
• and
• removing portions of the first insulation layer and the lightly doped impurity regions disposed between the masking regions and the insulation-filled trench regions to form an insulated gate, including the gate electrode and a gate insulator formed from the first insulation region, overlying the channel region and a pair of lightly-doped source and drain regions disposed adjacent to and on opposite sides of the channel region, and to expose sidewall portions of the insulation-filled trench regions;
• forming spaced apart insulating regions in the substrate, a respective one of which is disposed between the insulated gate and a respective one of the insulation-filled trench regions;
• and
• forming corresponding spaced apart source and drain regions on the spaced apart insulating regions.

A method for forming device isolation regions for separating adjacent integrated circuit field effect transistors in a semiconductor substrate, the method comprising the steps of:

• forming an insulation-filled trench region in the substrate;
• forming an insulated gate for each of the adjacent transistors on the semiconductor substrate, a respective one of which is spaced apart from and on opposite sides of the insulation-filled trench region
• forming insulating regions in the substrate between the insulated gates of the adjacent transistors and the insulation-filled trench region, wherein said step of forming insulating regions in the substrate comprises the steps of:
• forming barrier regions adjacent sidewall portions of the insulated gates and the insulation-filled trench region;
• and
• oxidizing exposed portions of the semiconductor substrate disposed between the barrier regions to produce spaced apart insulating regions, a respective one of which is disposed between the insulation-filled trench region and a respective one of the insulated gates;
• and
• forming active regions on the insulating regions.

A method for forming device isolation regions for separating adjacent integrated circuit field effect transistors in a semiconductor substrate, the method comprising the steps of:

• forming an insulation-filled trench region in the substrate;
• forming an insulated gate for each of the adjacent transistors on the semiconductor substrate, a respective one of which is spaced apart from and on opposite sides of the insulation-filled trench region;
• forming insulating regions in the substrate between the insulated gates of the adjacent transistors and the insulation-filled trench region;
• forming a polysilicon layer overlying the substrate;
• forming a masking material layer on the polysilicon layer;
• removing portions of the masking material layer to expose portions of the polysilicon layer overlying the insulated gates and the insulation-filled trench region and to leave masking material regions overlying the insulating regions;
• removing the exposed portions of the polysilicon layer overlying the insulated gates and the insulation-filled trench region to expose the insulated gates and the insulation-filled trench region;
• removing the masking material layer to expose regions of the polysilicon layer overlying the insulating regions;
• and
• implanting ions into the exposed regions overlying the insulating regions to form active regions overlying the insulating regions.

A method of fabricating an integrated circuit field effect transistor, the method comprising the steps of:

• etching a pair of trenches in a surface of a semiconductor substrate;
• forming an insulation layer on the substrate;
• removing portions of the insulation layer to expose surface portions of the semiconductor substrate disposed between the trenches and create a pair of insulation-filled trench regions;
• forming a first insulation layer on the substrate between the insulation-filled trench regions;
• forming a conductive layer on the first insulation layer;
• forming a second insulation layer on the conductive layer;
• removing portions of the second insulation layer and the conductive layer to form a gate protector, formed from the second insulation layer, overlying a gate electrode formed from the conductive layer and laterally separated from the insulation-filled trench regions by exposed portions of the first insulation layer;
• implanting ions into portions of the semiconductor substrate underlying the exposed portions of the first insulation layer to form a pair of lightly-doped impurity regions, a respective one of which is laterally disposed between the channel region and a respective one of the insulation-filled trench regions;
• forming a masking layer on the substrate;
• anisotropically removing portions of the masking layer to expose the gate protector and portions of the first insulation layer laterally disposed between the gate electrode and the insulation-filled trench regions and leave masking regions disposed adjacent sidewall portions of the gate electrode and the gate protector;
• removing portions of the first insulation layer and the lightly doped impurity regions disposed between the masking regions and the insulation-filled trench regions to form an insulated gate, including the gate electrode and a gate insulator formed from the first insulation layer, overlying a channel region and a pair of lightly-doped source and drain regions disposed adjacent to and on opposite sides of the channel region, and to expose sidewall portions of the insulation-filled trench regions;
• forming a barrier layer on the substrate;
• anisotropically etching the barrier layer to leave barrier regions disposed adjacent sidewall portions of the masking regions, the gate insulator, the lightly-doped source and drain regions and the insulation-filled trench regions;
• oxidizing exposed portions of the semiconductor substrate between the barrier regions to form an insulating region disposed between the lightly doped source region and one of the insulation-filled trench regions and an insulating region disposed between the lightly doped drain region and a second of the insulation-filled trench regions;
• removing the barrier regions to expose sidewall portions of the lightly doped source and drain regions;
• forming a polysilicon layer on the substrate;
• forming a masking material layer on the polysilicon layer;
• removing portions of the masking material layer to expose portions of the polysilicon layer overlying the insulated gate and the insulation-filled trench regions and to leave spaced apart masking material regions overlying the spaced apart insulating regions;
• removing exposed portions of the polysilicon layer overlying the insulated gate and the insulation-filled trench regions to expose the insulated gate and the insulation-filled trench regions;
• removing the masking material layer to expose spaced apart polysilicon regions overlying the spaced apart insulating regions;
• and
• implanting ions into the spaced apart polysilicon regions to form spaced apart source and drain regions overlying the spaced apart insulating regions.