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US 5,705,415 AGranted
Process for forming an electrically programmable read-only memory cell
AssigneeMotorola, Inc.
InventorsMarius K. Orlowski, Ko-Min Chang
Life of this patent
Estimating the term…
Abstract
A semiconductor device is formed having a floating gate memory cell (11) that has its channel region (33) oriented vertically with a portion of the channel region (33) that is not capacitively coupled to a floating gate (32). The memory cell (11) is less likely to be over-erased and may be programmed by source-side injection. The cell (11) may not need to be repaired after erasing. Less power may be consumed during programming compared to hot electron injection and Fowler-Nordheim tunneling.
Claims23
A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:
- forming a vertical edge adjacent to a primary surface of a semiconductor substrate;
- forming a first doped region and a second doped region, wherein:
- the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;
- the second doped region lies adjacent to the vertical edge and the primary surface, wherein a bottom of the second doped region at the vertical edge lies at a first elevation;
- and
- a channel region adjacent to the vertical edge that lies between the first and second doped regions, wherein the channel region includes a first portion adjacent to the first doped region and a second portion adjacent to the second doped region;
- forming a floating gate adjacent to the first portion of the channel region, wherein:
- the floating gate has a highest point adjacent to the vertical edge;
- and
- the highest point lies at a second elevation that is lower than and spaced apart from the first elevation;
- and
- the step of forming the floating gate is performed after the step of forming the vertical edge;
- forming a control gate adjacent to the first doped region;
- and
- forming a select gate adjacent to the control gate and the second portion of the channel region.
12 more elements
A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:
- forming a vertical edge adjacent to a primary surface of a semiconductor substrate;
- forming a first doped region, a second doped region and a third doped region, wherein:
- the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;
- the second doped region lies adjacent to the vertical edge and the primary surface, wherein a bottom of the second doped region at the vertical edge lies at a first elevation;
- a channel region adjacent to the vertical edge and lies between the first and second doped regions, wherein the channel region includes a first portion adjacent to the first doped region and a second portion adjacent to the second doped region;
- and
- the third doped region lies adjacent to the primary surface and is spaced apart from the second doped region;
- forming a floating gate adjacent to the first portion of the channel region, wherein:
- the floating gate has a highest point adjacent to the vertical edge;
- and
- the highest point lies at a second elevation that is lower than and spaced apart from the first elevation;
- and
- the step of forming the floating gate is performed after the step of forming the vertical edge;
- forming a control gate adjacent to the floating gate;
- and
- forming a select gate adjacent to the primary surface, the second doped region, and third doped region.
13 more elements
A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:
- forming a vertical edge adjacent to a primary surface of a semiconductor substrate;
- forming a first doped region, a second doped region and a third doped region, wherein:
- the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;
- the second doped region lies adjacent to the vertical edge and the primary surface;
- a channel region adjacent to the vertical edge and lies between the first and second doped regions;
- and
- the third doped region lies adjacent to the primary surface and is spaced apart from the second doped region;
- forming a floating gate adjacent to a first portion of the channel region, wherein the first portion is less than all of the channel region;
- forming a field isolation region after the step of forming the floating gate;
- forming a control gate adjacent to the floating gate but not the channel region;
- and
- forming a select gate adjacent to the primary surface, the second doped region, and third doped region.
9 more elements
A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:
- forming a vertical edge adjacent to a primary surface of a semiconductor substrate;
- forming a first doped region, a second doped region and a third doped region, wherein:
- the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;
- the second doped region lies adjacent to the vertical edge and the primary surface;
- a channel region adjacent to the vertical edge and lies between the first and second doped regions;
- and
- the third doped region lies adjacent to the primary surface and is spaced apart from the second doped region;
- forming a floating gate adjacent to a first portion of the channel region, wherein the first portion is less than all of the channel region;
- forming a field isolation region along the vertical edge and adjacent to the floating gate;
- forming a control gate adjacent to the floating gate but not the channel region;
- and
- forming a select gate adjacent to the primary surface, the second doped region, and third doped region.
9 more elements
A process for forming a semiconductor device including an electrically programmable read-only memory cell comprising the steps of:
- forming a vertical edge adjacent to a primary surface of a semiconductor substrate;
- forming a first doped region and a second doped region, wherein:
- the first doped region lies adjacent to the vertical edge and spaced apart from the primary surface;
- the second doped region lies adjacent to the vertical edge and the primary surface;
- and
- a channel region adjacent to the vertical edge and lies between the first and second doped regions;
- forming a floating gate adjacent to a first portion of the channel region;
- forming a field isolation region along the vertical edge and adjacent to the floating gate;
- forming a control gate adjacent to the first doped region;
- and
- forming a select gate adjacent to:
- the control gate;
- and
- a second portion of the channel region that is different from the first portion of the channel region.
11 more elements
Dependencies are inferred from the claim text.