Performing optical proximity correction with the aid of design rule checkers

A computer-implemented method of performing optical proximity correction on an integrated circuit layout design, the method comprising the following steps:

• (a) analyzing the integrated circuit layout design with a design rule checker to locate features of said integrated circuit layout design meeting a predefined criteria;
• (b) separating features that do not meet said predefined criteria from the integrated circuit layout design to define a partial layout design;
• (c) partitioning the partial layout design into a plurality of grid regions, some of the plurality of grid regions enclosing at least a portion of a feature in the partial layout design;
• (d) marching sequentially through each of the plurality of grid regions in the partial layout design;
• and
• (e) performing optical proximity correction for selected ones of the plurality of grid regions to produce a corrected partial layout design.

A computer-implemented optical proximity correction process comprising:

• (a) analyzing the integrated circuit layout design with a design role checker to locate features of said integrated circuit layout design meeting a predefined criteria;
• (b) partitioning the features meeting the predefined criteria into a plurality of grid regions, some of the plurality of grid regions enclosing at least a portion of the features meeting the predefined criteria;
• (c) marching sequentially through each of the plurality of grid regions;
• and
• (d) performing optical proximity correction in grid regions where at least the portion of the features meeting the predefined criteria are found in the marching.