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US 5,704,058 AGranted
Cache bus snoop protocol for optimized multiprocessor computer system
OwnerJohn E. Derrick, Christopher M. Herringinventors
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Abstract
A cache bus snoop protocol optimizes performance of a multiprocessor computer system with multiple level two caches by allocating windows of cache bus snoop activity on a need basis. When a cycle to cacheable address space is requested, the cache bus is granted only after the necessary snoop and write-back cycles are completed. During the snoop and write-back cycles, snoop activity by other devices in inhibited.
Claims3
A method of allocating windows of cache bus bandwidth for cache to cache and system snoop activity on a need basis to minimize impact on performance while maximizing memory page hit accesses comprising the steps of:
- providing an address space having cacheable and non-cacheable portions;
- providing a cycle request for access to a selected address within the address space;
- determining from the selected address if the cycle request requires snoop activity by determining whether the selected address is in the cacheable address space;
- allowing local bus and expansion bus activity to occur on the cache bus if the cycle request is for non-cacheable address space not requiring snoop activity;
- and
- delaying the cycle request if snoop activity is required until it can be determined that the necessary snoop and write-back cycles can be completed.
3 more elements
Dependencies are inferred from the claim text.