Counterflow pipeline processor architecture for semi-custom application specific IC's

A pipeline processor wherein instructions flow in a first direction and results flow in a second opposing direction in the pipeline, said pipeline processor comprising:

• program means for issuing instructions in said first direction in said pipeline, certain said instructions including user-defined operation codes;
• register means for storing and issuing results in said second opposing direction in said pipeline;
• plural pipeline stages connected between said program and said register means, at least one pipeline stage comprising instruction latch means connected to receive and issue instructions in said first direction, result latch means connected to receive and issue result data in said second opposing direction, logic means coupling said instruction latch means and result latch means for determining when result data and instructions are associated and further responsive to a predetermined pipeline operation code to execute a received instruction, said logic means being non-responsive to a user-defined operation code that is related to said received instruction, to execute said received instruction, said at least one pipeline stage further including conversion means for determining a correspondence between a user-defined operation code and said predetermined pipeline-operation code and, upon occurrence of said correspondence, enabling said logic means to execute at least one operation with respect to said received instruction or result;
• and
• processing siding means coupled to at least some said plural pipeline stages for performing logical operations on said result data in accordance with pipeline operation codes.