Bit processing unit for performing complex logical operations within a single clock cycle

A microprocessor for executing instructions within an instruction steam, comprising:

• instructions register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes:
• a shift functional unit having a first input and a second input connected to said instruction register and an output, and
• a NOT gate having an input connected to said output of said shift functional unit and an output, and
• an AND gate having a first input connected to said output of said NOT gate, a second input connected to said register file representing an input word, and an output, said output representing the result of a clear-bit field operation that resets specified bits of said input word to zero and leaves all other bits of said input word intact.

A microprocessor for executing instructions with an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes:
• a shift functional unit having a first input and a second input connected to said instruction register and an output, and
• an AND gate having a first input connected to said output of said shift functional unit, a second input connected to said register file representing an input word, and an output, said output representing the result of "an isolate bit-field" operation that resets all bits of said input word except specified bits of said input word.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes:
• a shift functional unit having a first input and a second input connected to said instruction register and an output, said first input representing a first input word,
• a multiplexer having a first input connected to said register file, a second input and a control input connected to said instruction register, and an output,
• a shift/rotate functional unit having a first input connected to said register file representing a second input word, a control input connected to said output of said multiplexer and an output,
• a first AND gate having a first input connected to said output of said shift functional unit, a second input connected to said output of said shift/rotate functional unit, and an output,
• a second AND gate having a first input connected to said register file, a second input connected to said output of said shift functional unit, and an output, and
• an OR gate having a first input connected to said output of said first AND gate, a second input connected to said output of said second AND gate, and an output, said output representing the result of "a load bit-field" operation that replaces specified bits of said second input word with corresponding bits of said first input word, wherein all other bits of said output are copied from said second input word.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes:
• a multiplexer having a first input connected to said register file, a second input connected to said instruction register, a control input connected to said instruction register, and an output, and
• a shift/rotate functional unit having a first input connected to said register file, a second input connected to said output of said multiplexer, and an output, said output representing a result of a shift and rotate operation that shifts or rotates said first input of said shift/rotate functional unit a specified number of bit positions toward the most significant bit of said first input.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before executing;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes:
• a shift functional unit having a first input and a second input connected to said instruction register and an output,
• a multiplexer having a first input connected to said register file, a second input and a control input connected to said instruction register, and an output,
• a shift/rotate functional unit having a first input connected to said register file representing an input word, a control input connected to said output of said multiplexer and an output, and
• an AND gate having a first input connected to said output of said shift functional unit, a second input connected to said output of said shift/rotate functional unit, and an output, said output representing the result of "an extract bit-field" operation that moves specified bits of said input word within said input word and resets all other bits of said input word to zero.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes:
• a shift functional unit having a first input and a second input connected to said instruction register and an output,
• a first multiplexer having a first input connected to said register file, a second input and a control input connected to said instruction register, and an output,
• a shift/rotate functional unit having a first input connected to said register file representing an input word, a control input connected to said output of said first multiplexer and an output,
• a first AND gate having a first input connected to said output of said shift functional unit, a second input connected to said output of said shift/rotate functional unit, and an output,
• a second multiplexer having a first input connected to said output of said first AND gate, a second input and third input connected to said instruction register, and an output,
• a second AND gate having a first input connected to said register file, a second input connected to said output of said shift functional unit, and an output,
• an XOR gate having a first input connected to said output of said second multiplexer, a second input connected to said output of said second AND gate, and an output, and
• an OR gate having an input connected to said output of said XOR gate and an output, said output representing the result of "a compare bit-field" operation that sets a match flag register.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing a clear bit-field operation that resets specified bits of an input word to zero and leaves all other bits of said input word intact.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing an isolate bit-field operation.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing an extract bit-field operation that moves specified bits of an input word within said input word and resets all other bits of said input word to zero.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing a load bit-field operation.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing a compare bit-field operation.

A microprocessor for executing instructions within an instruction stream, comprising:

• an instruction register that functions as a queue for instructions before execution;
• a register file having a plurality of general purpose registers;
• an arithmetic logic unit, connected to said register file and said instruction register, that executes said instructions having arithmetic operations;
• and
• a bit processing unit, connected to said register file and said instruction register, said bit processing unit having a shift functional unit, a shift/rotate functional unit, and a merge functional unit that contain digital logic for performing a Boolean operation, configured to execute said instructions having complex logical operations within a single clock cycle, wherein said bit processing unit includes means for performing a load literal field operation that stores a value stored in a literal field of an instruction to a target field within a word, wherein bits outside said target field are cleared to zero.