Mask programmable security system for a data processor and method therefor

A method for providing security for a data processor, comprising the steps of:

• i. receiving a plurality of signals using a bus interface circuit;
• ii. retrieving a first stored address value from a first one of a plurality of mask registers;
• iii. retrieving a first stored data value from the first one of the plurality of mask registers;
• iv. comparing the first stored address value with a first address value of the plurality of signals;
• v. comparing the first stored data value with a first data value of the plurality of signals;
• vi. asserting a first match signal when the first stored address value is equal to the first address value of the plurality of signals and when the first stored data value is equal to the first data value of the plurality of signals;
• vii. executing step ii, when one of the first stored address value is not equal to the first address value of the plurality of signals and the first stored data value is not equal to the first data value of the plurality of signals;
• viii. negating a secure signal when the first match signal is asserted;
• ix. retrieving a next stored address value from a next one of the plurality of mask registers;
• x. retrieving a next stored data value from the next one of the plurality of mask registers;
• xi. comparing the next stored address value with a next address value of the plurality of signals;
• xii. comparing the next stored data value with a next data value of the plurality of signals;
• xiii. asserting a next match signal when the next stored address value is equal to the next address value of the plurality of signals, when the next stored data value is equal to the next data value of the plurality of signals, and when a previous match signal was asserted;
• xi. executing step ii. when one of the next stored address value is not equal to the next address value of the plurality of signals and the next stored data value is not equal to the next data value of the plurality of signals;
• xv. executing steps x. through xv. for a predetermined number of repetitions;
• and
• xvi. negating the secure signal when the first match signal is asserted and when each of a plurality of next match signals is asserted.