Power-on-reset and watchdog circuit and method

A method for resetting a microprocessor having a reset input terminal and a watchdog output terminal, comprising the steps of:

• detecting a microprocessor error signal on the watchdog output terminal of the microprocessor and generating an oscillating monitor error signal in response thereto;
• detecting the oscillating monitor error signal at a first node and;
• generating a reset enable signal at a second node in response thereto, wherein
• (1) the second node is connected to the reset input terminal of the microprocessor, and
• (2) the first node is different from the second node.

A circuit, comprising:

• a) a microprocessor having
• i) a reset input (50) and;
• ii) an error output (60), which outputs a pulse train in the absence of an error condition;
• b) an oscillator,
• i) comprising
• A) a transistor network for delivering an oscillating signal to said reset input (50);
• B) a monitor means which detects said pulse train and, in response, inhibits the transistor network from oscillating.

A circuit for applying pulses to a first pin (50) of a microprocessor, when the microprocessor ceases producing pulses at a second pin (60), comprising:

• a) three transistors;
• and
• b) circuit means, which includes resistors and capacitors, comprising
• i) nodes N1 and N2, connected to a first of said transistors;
• ii) nodes N2 and N3, connected to a second of said transistors;
• iii) nodes N5 and N7, connected to a third of said transistors;
• iv) a connection for applying signals at node N3 to said first pin (50);
• and
• v) a connection for applying signals at said second pin (60) to node N1,
• wherein a train of pulses is produced at node N3 when a train of pulses at node N1 terminates.

An electronic circuit, comprising:

• a) a microprocessor (40), having a reset input (50) and an error output (60);
• b) a monitoring-and-reset circuit, consisting essentially of the following:
• i) a power line and a ground line;
• ii) a first resistor (R1) connecting between a node N1 and the ground line;
• iii) a first NPN transistor (Q1), having
• A) its base connected to the node N1;
• B) its collector connected to a node N2;
• C) its emitter connected to the around line;
• iv) a parallel RC network (R2, C1), connecting between the node N2 and the power line;
• v) a second NPN transistor (Q2), having
• A) its base connected to the node N2;
• B) its collector connected to a node N3;
• C) its emitter connected to the ground line;
• vi) a third resistor (R3) connecting between the node N3 and the power line;
• vii) a second capacitor (C2) connecting between the node N3 and the ground line;
• viii) a fourth resistor (R4) connecting between the node N3 and a node N7;
• ix) a PNP transistor (Q3), having
• A) its base connected to the node N7;
• B) its collector connected to a node N5;
• C) its emitter connected to the power line;
• x) a fifth resistor (R5), connecting between the node N5 and the ground line;
• xi) a sixth resistor (R6), connecting between the node N5 and a node N6;
• xii) a third capacitor (C3), connecting between the node N6 and the ground line;
• xiii) a seventh resistor (R7), connecting between the node N6 and the node N1;
• xiv) a fourth capacitor (C4), connecting between the node N1 and the error output (60);
• and
• xv) a line connecting between node N3 and the reset input (50),
• wherein node N3 delivers an oscillating signal to the reset input (50) in the absence of a pulse train at the error output (60), and wherein node N3 delivers a DC signal to the reset input (50) when a pulse train exists at the error output (60).