Method and circuit for initializing a data processing system
AssigneeMotorola, Inc.
InventorJoseph C. Circello
Life of this patent
Estimating the term…
Abstract
A data processor (3) executes a breakpoint operation before an exception processing routine for a reset operation is initiated. When an External Reset signal is asserted and subsequently negated, a window of time exists in which data processor (3) is quiescent before beginning an actual reset exception processing routine. If an external breakpoint signal, BKPT is asserted during a quiescent time by external development system (7), data processor (3) downloads a target memory value into a memory (6) such that any hardware register configuration may be performed.
Claims18
A data processor comprising:
- a reset input, a reset control input, and a data input;
- a circuit portion specifying a normal reset response;
- a memory area for storing at least one data processor configuration parameter;
- a central processor unit coupled to the reset input, the reset control input, the circuit portion, and the memory area, wherein, when an asserted reset signal is received by the reset input, the central processor trait enters a quiescent state;
- if during the a quiescent state, an asserted reset control signal occurs the memory area is modified based on a data received by the data input;
- if during the quiescent state the reset control signal is not asserted, the central processor continues execution based on the circuit portion.
A method for providing a data processor comprising the steps of:
- providing an input circuit for receiving a reset signal, a reset control signal, and a data signal;
- providing a memory location coupled to the input circuit;
- providing a central processor unit coupled to the input circuit and the memory location, wherein when the reset signal is asserted the central processor unit enters a quiescent state, if the reset control signal is asserted during the quiescent state the central processor enters a first state allowing a value of the data signal to be stored at the memory location, and if the reset control signal is not asserted during the quiescent state the central processor enters a second state of operation.
A data processor comprising:
- a central processor trait having a memory location;
- an input circuit having an first terminal coupled to the central processor unit for receiving a data value, and a second terminal coupled to the central processor unit, and a reset terminal, wherein when asserted the reset terminal initializes a reset cycle which comprises a first state and a second state, during the first state the central processor is in a quiescent state and during the second state the central processor is in normal reset state, if during the first state an asserted signal is received by the second input terminal the data processor is placed into a configuration mode allowing the data value to be written to the memory location, otherwise, if during the first state no asserted signal is received by the second input terminal the data processor continues operation in the second state.
Dependencies are inferred from the claim text.