Semiconductor photonic integrated circuit and fabrication process therefor

Abstract

On a surface of an n-InP substrate, a mask of SiO.sub.2 layer wide in an active region and narrow in a passive region and having a constant gap width. In a waveguide region defined between the masks, a waveguide structure constituted of an n-InGaAsP guide layer, an undoped InGaAsP optical waveguide layer and a p-InP clad layer is selectively grown to form. Again, utilizing SiO.sub.2 layer, a mask is formed on the surface of the p-InP layer in the active region and a pair of masks defining the waveguide structure is formed in a the passive region, and high resistance InP layer is grown. Also, in the active region, a p-InP layer, a p-InGaAs contact layer are selectively grown. By forming SiO.sub.2, a window is formed to form p-side electrode. An n-type electrode is formed on the back surface of the substrate, By this, a device having an optical loss in the active region and passive region becomes low, a coupling coefficient between both regions is high. Also, an element capacitance can become small to enable high speed operation.

Dependencies are inferred from the claim text.