External memory control circuit for sound field processing digital signal processor

An external memory control circuit for a digital signal processor adapted to execute an algorithm used in sound field processing for an input signal, the algorithm processing a first control signal and a second control signal, and to control a memory unit for obtaining a signal delay required in a computational operation for the sound field processing, comprising:

• memory buffer control means for receiving the first control signal and the second control signal upon executing the algorithm, for controlling reading of data recorded in the memory unit in accordance with the first control signal and controlling recording of data externally input to the memory unit in accordance with the second control signal;
• memory buffer means for buffering recorded data output from the memory unit and data to be externally input to the memory unit under the control of the memory buffer control means;
• switching means for receiving a third control signal when a power is first supplied to the digital signal processor or when a change of the algorithm is made, and for outputting a selection control signal in accordance with the third control signal;
• multiplexing means for selecting one of a data value output from the memory buffer means and a muting data value in accordance with the selection control signal from the switching means and outputting the thusly selected data value;
• and
• direction selecting means for outputting the data value output from the multiplexing means to an internal data bus and for outputting data from an internal data bus to the memory buffer means under control of the memory buffer control means.