Clock recovery circuit employing delay-and-difference circuit and pulse-sequence detection

A clock recovery circuit for recovering a clock signal from a differential phase signal, comprising;

• a delay-and-difference circuit for receiving said differential phase signal, delaying said differential phase signal by a certain first time to obtain a delayed signal, and taking a difference between said differential phase signal and said delayed signal to obtain a double differential phase signal;
• a first comparator coupled to said delay-and-difference circuit, for generating a first pulse when said double differential phase signal matches a certain positive level;
• a second comparator coupled to said delay-and-difference circuit, for generating a second pulse when said double differential phase signal matches a certain negative level;
• a third comparator coupled to said delay-and-difference circuit, for generating a third pulse when said double differential phase signal matches a zero level;
• a gate-signal generating circuit coupled to said first comparator and said second comparator, for activating a gate signal for a certain second time when said first pulse is followed by said second pulse within a certain third time, and for activating said gate signal for said second time when said second pulse is followed by said first pulse within said third time;
• a delay circuit coupled to said third comparator, for delaying said third pulse by a certain fourth time to obtain a delayed pulse;
• a gate circuit coupled to said delay circuit, for outputting said delayed pulse as a timing pulse if said gate signal is active;
• and
• a digital phase-locked loop coupled to said gate circuit, for generating said clock signal and adjusting said clock signal in phase so as to synchronize a certain transition of said clock signal with said timing pulse.

A method of recovering a clock signal from a differential phase signal, comprising the steps of:

• delaying said differential phase signal by a certain first time to obtain a delayed differential phase signal;
• taking a difference between said differential phase signal and said delayed differential phase signal to obtain a double differential phase signal;
• comparing said double differential phase signal with a plurality of levels, and generating respective pulse signals when said double differential phase signal matches said levels;
• detecting certain sequences of said pulse signals;
• activating a gate signal for a certain second time when said certain sequences are detected;
• delaying one of said pulse signals by a certain third time to obtain a delayed pulse signal;
• outputting said delayed pulse signal as a timing signal when said gate signal is active;
• and
• generating said clock signal and locking said clock signal in phase to said timing signal.