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US 5,703,884 AGranted
Scanning pass test circuit
AssigneeNEC Corporation
InventorHideharu Ozaki
Life of this patent
Estimating the term…
Abstract
A shift register constituting a scanning pass test circuit is divided into a plurality of groups, and bypass selectors are inserted into the divided positions of the shift register. A latch circuit is connected to each of the clock signal terminals of the flip-flop circuits which are disposed at the first stage of the flip-flop circuit groups.
Claims5
A scanning pass test circuit comprising:
- a scan-in terminal;
- a scan-out terminal;
- a plurality of flip-flops connected together in series, wherein said plurality of flip-flops are divided into groups to form a first shift register and a second shift register;
- first means for selectively connecting said scan-in terminal with an input node of either of said first and second shift registers for shifting input data inputted to said scan-in terminal;
- second means for selectively connecting said scan-out terminal with an output node of said first shift register when said first means connects said scan-in terminal with an input of said first shift register, and for selectively connecting said scan-out terminal with an output node of said second shift register when said first means connects said scan-in terminal with an input of said second shift register;
- and
- third means for supplying a shift clock to said first shift register and not supplying said shift clock to said second shift register when said first means connects said scan-in terminal with said input of said first shift register.
4 more elements
A scanning pass test circuit for testing a combination circuit comprising:
- a shift register connected to an output selector, wherein said output selector includes a first input connected with an output of said shift register and a second input connected with an input of said shift register;
- and
- shift clock supply means, attached to said shift register for supplying a series of shift clocks thereto,
- wherein said shift clock supply means supplies said shift clock to said and when said output selector selects said first input and does not supply said shift clock to said shift register when said output selector selects said second input.
1 more element
Dependencies are inferred from the claim text.