US 5,703,871 A · Facilities data link handler in a performance monitoring and test system

Abstract

A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

Claims11

Dependent claims

A Facilities Data Link handler, comprising:

an input register for storing at least a portion of a DS1 FDL packet;
a counter for counting bits stored in the register;
and
a circuit, receiving the stored portion and count, capable of assembling a plurality of DS1 FDL packet portions into an FDL packet, wherein FDL packets from a plurality of asynchronous DS1 signals are assembled.

1 more element

Dependencies are inferred from the claim text.

Facilities data link handler in a performance monitoring and test system

Life of this patent

Facilities data link handler in a performance monitoring and test system

Life of this patent

Abstract

Claims11