US 5,703,832 A · t.sub.RAS protection circuit

Abstract

Circuits and methods are disclosed to protect dynamic random access memory cell data from being destroyed when the minimum t.sub.RAS specification is not being adhered to, by holding off the already issued Row Precharge command until such time that t.sub.RAS is satisfied. The memory cell data is getting protected by providing a timing reference circuit with a delay .tau., where this delay tracks the bitline restore time of the memory array cell, a row activation control logic which holds off the row precharge cycle until time .tau. has elapsed, insuring that the bitline signals are fully restored, and an internal circuitry which provides a high isolation voltage for the bitline isolation devices and for a charging transistor in the timing reference circuit.

Claims18

Dependent claims

A method of protecting data in a memory, comprising:

receiving a row activation command to begin an active period in said memory;
generating a restore complete signal upon completion of restoring bit lines in said memory, wherein said restoring requires a time .tau.;
receiving and registering a row precharge command, wherein said row precharge command may be received prior to completion of said bit line restoring;
and
using said restore complete signal and the registered row precharge command to initiate precharging of said bit lines.

2 more elements

A memory array t.sub.RAS protection circuit comprising:

a timing reference circuit to track a bitline restore time of a memory array cell, with a first input, a second input, and an output, said output of said timing reference circuit providing a logical one voltage level and a logical zero voltage level;
a row activation control logic to produce a row control timing of a memory array, with a first input, a second input, and an output, said second input of said row activation control logic connected to said output of said timing reference circuit, said output of said row activation control logic providing a logical one voltage level and a logical zero voltage level;
a row command register issuing a logical one voltage level during an active period of a memory cycle and a logical zero voltage level during an inactive period of said memory cycle connected to said first input of said row activation control logic;
and
an internal circuitry to produce a high isolation voltage and a gating signal for said timing reference circuit, with an input, a first output, and a second output, said input of said internal circuitry connected to said output of said row activation control logic, said first output of said internal circuitry connected to said first input of said timing reference circuit, and said second output of said internal circuitry connected to said second input of said timing reference circuit.

2 more elements

A method of protecting a memory array t.sub.RAS time, comprising:

providing a timing reference circuit to track a restore time of bitlines of a memory array cell, with a first input, a second input, and an output TR.sub.restore, said output of said timing reference circuit providing a logical one voltage level and a logical zero voltage level;
providing a row activation control logic to produce a row control timing of a memory array, with a first input RRA, a second input, and an output RA, said second input of said row activation control logic connected to said output of said timing reference circuit, said output of said row activation control logic providing a logical one voltage level and a logical zero voltage level;
providing a row command register issuing a logical one voltage level during an active period of a memory cycle and a logical zero voltage level during an inactive period of said memory cycle, said row command register connected to said first input of said row activation control logic;
and
providing an internal circuitry to produce a high isolation voltage and a gating signal for said timing reference circuit, with an input, a first output, and a second output, said input of said internal circuitry connected to said output of said row activation control logic, said first output of said internal circuitry connected to said first input of said timing reference circuit, and said second output of said internal circuitry connected to said second input of said timing reference circuit.

2 more elements

Dependencies are inferred from the claim text.

t.sub.RAS protection circuit

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t.sub.RAS protection circuit

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Abstract

Claims18