US 5,703,830 AGranted

Syncronous dynamic semiconductor memory device using pipelined multi-bit prefetch architecture

AssigneeNEC Corporation

InventorTakai Yasuhiro

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Abstract

In a synchronous dynamic semiconductor memory device, a plurality of data paths, each of which is formed by a column decoder, a sense amplifier and a first-stage data amplifier, are provided between a column address buffer having a burst counter function and a second-stage data amplifier which is further connected to a data latch circuit.

Claims4

Dependent claims

A synchronous dynamic semiconductor memory device comprising:

a column address buffer including burst counters and generating first and second series of address signals in synchronization with every two clock cycles of a clock signal;
a first column decoder, connected to said column address buffer, for decoding said first series of address signals in synchronization with every two clock cycles of said clock signal;
a second column decoder, connected to said column address buffer, for decoding said second series of address signals in synchronization with every two clock cycles of said clock signal;
a first sense amplifier, connected to said first column decoder, for amplifying a first data signal in accordance with a first column switch signal of said first column decoder and generating a voltage at a first read bus;
a second sense amplifier, connected to said second column decoder, for amplifying a second data signal in accordance with a second column switch signal of said second column decoder and generating a voltage at a second read bus;
a first first-stage data amplifier, connected to said first read bus, for amplifying the voltage of said first read bus and transmitting an amplified voltage of said first read bus to a read/write bus in synchronization with every two clock cycles of said clock signal;
a second first-stage data amplifier, connected to said second read bus, for amplifying the voltage of said second read bus and transmitting an amplified voltage of said second read bus to said read/write bus in synchronization with every two clock cycles of said clock signal, said second first-stage data amplifier being operated time-divisionally with said first first-stage data amplifier;
a second-stage data amplifier, connected to said read/write bus, for amplifying a voltage of said read/write bus in synchronization with every one clock cycle of said clock signal;
and
a data latch circuit, connected to said second-stage data amplifier, for latching an output of said second-stage data amplifier in synchronization with every one clock cycle of said clock signal to generate an output data signal.

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Dependencies are inferred from the claim text.

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Abstract

A synchronous dynamic semiconductor memory device comprising:

a column address buffer including burst counters and generating first and second series of address signals in synchronization with every two clock cycles of a clock signal;
a first column decoder, connected to said column address buffer, for decoding said first series of address signals in synchronization with every two clock cycles of said clock signal;
a second column decoder, connected to said column address buffer, for decoding said second series of address signals in synchronization with every two clock cycles of said clock signal;
a first sense amplifier, connected to said first column decoder, for amplifying a first data signal in accordance with a first column switch signal of said first column decoder and generating a voltage at a first read bus;
a second sense amplifier, connected to said second column decoder, for amplifying a second data signal in accordance with a second column switch signal of said second column decoder and generating a voltage at a second read bus;
a first first-stage data amplifier, connected to said first read bus, for amplifying the voltage of said first read bus and transmitting an amplified voltage of said first read bus to a read/write bus in synchronization with every two clock cycles of said clock signal;
a second first-stage data amplifier, connected to said second read bus, for amplifying the voltage of said second read bus and transmitting an amplified voltage of said second read bus to said read/write bus in synchronization with every two clock cycles of said clock signal, said second first-stage data amplifier being operated time-divisionally with said first first-stage data amplifier;
a second-stage data amplifier, connected to said read/write bus, for amplifying a voltage of said read/write bus in synchronization with every one clock cycle of said clock signal;
and
a data latch circuit, connected to said second-stage data amplifier, for latching an output of said second-stage data amplifier in synchronization with every one clock cycle of said clock signal to generate an output data signal.

7 more elements