Method and structure for generating a boosted word line voltage and a back bias voltage for a memory array

A semiconductor memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the memory comprising:

• a voltage generation circuit coupled to the first and second voltage supplies, the voltage generation circuit generating a substantially constant boosted voltage which exceeds the first supply voltage;
• a driver circuit coupled to the voltage generation circuit and the word line, the driver circuit being adapted to selectively apply the boosted voltage to the word line;
• a charge pump circuit which generates an output voltage in response to a master clock signal;
• a regulator circuit coupled to the charge pump circuit, wherein the regulator circuit enables the charge pump circuit when the output voltage is less than the boosted voltage and wherein the regulator circuit disables the charge pump circuit when the output voltage is greater than the boosted voltage;
• and
• a clock synchronization circuit for receiving an external clock signal, and in response, generating the master clock signal, the master clock signal being synchronized with the external clock signal.

A semiconductor memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the memory comprising:

• a voltage generation circuit coupled to the first and second voltage supplies, the voltage generation circuit generating a substantially constant boosted voltage which exceeds the first supply voltage;
• a driver circuit coupled to the voltage generation circuit and the word line, the driver circuit being adapted to selectively apply the boosted voltage to the word line;
• a second voltage generation circuit coupled to the first and second voltage supplies, the second voltage generation circuit generating a substantially constant bias voltage which is less than the second supply voltage, wherein the second voltage generation circuit comprises:
• a charge pump circuit for generating an output voltage in response to a clock signal;
• a regulator circuit coupled to the charge pump circuit, wherein the regulator circuit enables the charge pump circuit when the output voltage is greater than the bias voltage and wherein the regulator circuit disables the charge pump circuit when the output voltage is less than the bias voltage;
• a ring oscillator circuit for generating a start-up clock signal;
• and
• a clock selector circuit which provides the start-up clock signal to the charge pump circuit during power-on of the memory, and provides the master clock signal to the charge pump circuit during normal operation of the memory.

A semiconductor memory fabricated on a substrate, the memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the memory comprising:

• a first voltage generation circuit coupled to the first and second voltage supplies, the voltage generation circuit generating a substantially constant boosted voltage which is less than the second supply voltage;
• and
• a driver circuit coupled to the first voltage generation circuit and the word line, the driver circuit being adapted to selectively apply the boosted voltage to the word line;
• and
• a second voltage generation circuit coupled to the first and second voltage supplies, the second voltage generation circuit generating a substantially constant bias voltage which is greater than the first supply voltage, the second voltage generation circuit being coupled to the substrate, thereby applying the bias voltage to the substrate.

A method of operating a semiconductor memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the method comprising the steps of:

• generating a substantially constant boosted voltage which exceeds the first supply voltage;
• applying the boosted voltage to a driver circuit which is coupled to the word line, wherein the step of generating the boosted voltage comprises the steps of:
• applying a master clock signal to a voltage generation circuit, wherein the voltage generation circuit generates the boosted voltage in response to the master clock signal;
• and
• regulating the boosted voltage by controlling the application of the master clock signal to the voltage generation circuit;
• receiving an external clock signal;
• and
• generating the master clock signal in response to the external clock signal, the master clock signal being synchronized with the external clock signal.

A method of operating a semiconductor memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the method comprising the steps of:

• generating a substantially constant boosted voltage which exceeds the first supply voltage;
• applying the boosted voltage to a driver circuit which is coupled to the word line, wherein the step of generating the boosted voltage comprises the steps of:
• applying a master clock signal to a voltage generation circuit, wherein the voltage generation circuit generates the boosted voltage in response to the master clock signal;
• and
• regulating the boosted voltage by controlling the application of the master clock signal to the voltage generation circuit;
• and
• generating a substantially constant bias voltage which is less than the second supply voltage in response to the master clock signal.

A method of operating a semiconductor memory fabricated on a substrate, the memory having a word line, a first voltage supply for providing a first supply voltage, and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the method comprising the steps of:

• generating a substantially constant boosted voltage which is less than the second supply voltage;
• applying the boosted voltage to a driver circuit which is coupled to the word line, wherein the step of generating the boosted voltage comprises the steps of:
• applying a master clock signal to a voltage generation circuit, wherein the voltage generation circuit generates the boosted voltage in response to the master clock signal;
• and
• regulating the boosted voltage by controlling the application of the master clock signal to the voltage generation circuit;
• and
• generating a substantially constant bias voltage which is greater than the first supply voltage in response to the master clock signal;
• and
• applying the bias voltage to the substrate.