Semiconductor integrated circuit device having a leakage current reduction means
AssigneeHitachi, Ltd.
InventorsTakesada Akiba, Goro Kitsukawa
Life of this patent
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Abstract
A circuit and method for reducing the leakage current drawn by a transistor when it is inactive. In a first implementation, a circuit selectively drives the gate of a transistor to a voltage level above a source voltage. As a result, the gate-source voltage is reversed and the leakage current flowing through the transistor is substantially reduced. In a second implementation, a circuit selectively biases the well of a transistor to a voltage level above a normal bias voltage. As a result, the voltage-current characteristics of the transistor are modified so that the leakage current is substantially eliminated.
Claims21
An output circuit comprising:
- a first terminal for receiving a positive power supply voltage;
- a second terminal for receiving a negative power supply voltage;
- and
- a first inverter comprising a PMOS transistor and an NMOS transistor connected in series between said first and second terminals;
- wherein, in a normal mode, an input signal to said first inverter, supplied to gates of said PMOS and NMOS transistors, has a first voltage level corresponding to said negative power supply voltage and a second voltage level corresponding to said positive power supply voltage, and
- wherein, in a standby mode, said input signal to said first inverter has a third voltage level being higher than the level of said positive power supply voltage.
An output circuit comprising:
- a first terminal for receiving a positive power supply voltage;
- a second terminal for receiving a negative power supply voltage;
- and
- an inverter comprising a PMOS transistor and an NMOS transistor connected in series between said first and second terminals,
- wherein, in a normal mode, a first voltage level corresponding to said power supply voltage is applied to a well of said PMOS transistor, and
- wherein, in a stand-by mode, a second voltage level is applied to said well of said PMOS transistor, said second voltage level being higher than a level of said positive power supply voltage.
A circuit for reducing leakage current in a transistor, the circuit comprising an output transistor having a gate connected to an input of the circuit, a drain connected to an output of the circuit and a source connected to a first power supply, and means for selectively disconnecting the gate from the input and connecting the gate to a second power supply, wherein a voltage level of the second power supply is greater than a voltage level of the first power supply.
A method for selectively switching a PMOS transistor between a normal mode in which the PMOS transistor operates in a conventional manner and a standby mode in which a leakage current of the PMOS transistor is significantly reduced, the method comprising selectively connecting a gate of the PMOS transistor to a power supply having a voltage level that is greater than a source voltage of the PMOS transistor.
A method for selectively switching an NMOS transistor between a normal mode wherein the NMOS transistor operates in a conventional manner and a standby mode wherein a leakage current of the NMOS transistor is significantly reduced, the method comprising selectively connecting a gate of the transistor to a power supply having a voltage level that is less than a source voltage of the NMOS transistor.
A circuit for reducing leakage current in a transistor, the circuit comprising an output transistor having a gate connected to an input of the circuit, a drain connected to an output and a source connected to a first power supply, and means for selectively connecting a well of the output transistor to either the first power supply or a second power supply, wherein a voltage level of the second power supply is greater than a voltage level of the first power supply.
A method for selectively switching an output transistor between a normal mode wherein the output transistor operates in a conventional manner and a standby mode wherein a leakage current through the output transistor is reduced comprising selectively connecting a well of the output transistor between two separate power supplies.
A semiconductor memory comprising:
- a memory array;
- a peripheral circuit coupled to said memory array;
- and
- a step-up circuit generating a second power-supply voltage higher than a first power-supply voltage,
- wherein said peripheral circuit includes an output transistor having a gate coupled to an input terminal, a drain coupled to an output terminal and a source receiving said first power-supply voltage and a switch circuit which supplies said second power-supply voltage to said gate with said gate disconnected from said input terminal.
A semiconductor memory comprising:
- a memory array;
- a decoder coupled to said memory array;
- a control circuit which outputs a control signal to indicate whether said decoder is in either normal operation state or stand-by state;
- and
- a step-up circuit which generates a second power-supply voltage hither than a first power-supply voltage,
- wherein said decoder comprises an output circuit having a PMOS transistor with a gate coupled to an input terminal, a drain coupled to an output terminal and a source receiving said first power-supply voltage and a switch circuit which supplies said second power-supply voltage to said gate with said gate disconnected from said input terminal.
Dependencies are inferred from the claim text.