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US 5,703,824 AGranted
Semiconductor memory device
AssigneeNEC Corporation
InventorSatoshi Isa
Life of this patent
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AssigneeNEC Corporation
InventorSatoshi Isa
Estimating the term…
A semiconductor memory device capable of restricting an increase of a gate capacitance of a substitution address program circuit connected to an address bus and reducing charge/discharge current of the substitution address program circuit to reduce current consumption of a chip and to restrict an increase of time from a time instance when an address signal is input to a time instance when a redundancy selection signal is output is provided. Addresses containing defects are programmed by fuses 2 and a node PRE has a potential swung between a first potential which is lower than a power source potential and higher than a reference potential VREF which is set to an intermediate potential between the power source potential and a ground potential and a second potential lower than the reference potential and higher than the ground potential. A differential amplifier 10 determines a coincidence or non-coincidence of the input address with the program address by comparing the potential of the node PRE with the reference potential and generates a redundancy determination signal RED correspondingly thereto.
A semiconductor memory devices equipped with a redundancy circuit which produces a redundancy selection signal indicative of whether or not an input address is coincident with a programmed address, said redundancy circuit comprising:
A semiconductor memory device with a substitution address program circuit comprising:
A semiconductor memory device comprising a power line supplied with a power potential, first and second nodes, a precharging circuit coupled to said power line and said first and second nodes, said precharging circuit responding to a precharge control signal and precharging said first node to a first voltage that is lower than said power potential and said second node to a reference potential, an address detection circuit coupled between said first and second nodes and forming an electrical path therebetween when an input address is coincident with a programmed address, said address detection circuit maintaining an electrical isolation between said first and second nodes when said input address is non-coincident with said programmed address, and a comparator coupled to said first node and supplied with a second voltage that has an intermediate potential between said power and reference potentials, said comparator comparing a potential to said first node with said second voltage.
Dependencies are inferred from the claim text.