US 5,703,823 A · Memory device with programmable self-refreshing and testing methods therefore

Abstract

A programmable self-time refresh circuit for a semiconductor memory and methods for programming the self-refresh rate for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.

Claims20

Dependent claims

A data processing system comprising:

processing means for processing data;
and
at least one memory means for storing data, said at least one memory means being electrically coupled to the processing means, each at least one memory means including a memory array accessed through word line and bit lines, and a refresh circuit integrated with the memory array, said refresh circuit including
a self-timed oscillator that outputs a clocking signal,
a programmable non-volatile frequency divider coupled to receive said clocking signal and output therefrom a signal transition based upon a programmed frequency division, and
refresh control logic connected to the programmable non-volatile frequency divider for receiving the signal transition output therefrom, said refresh control logic responding thereto by refreshing a portion of the memory array.

3 more elements

A method for non-invasively testing self-refreshing of a semiconductor memory device having a memory array and a refresh circuit integrated therewith for refreshing the memory array, said method comprising the steps of:

(i) determining a refresh characteristic during standard operation of the semiconductor memory device;
and
(ii) using the parameter determined in said step (i) to determine at least one of a wait state interval and a rate of self-refresh of the memory array.

Dependencies are inferred from the claim text.

Memory device with programmable self-refreshing and testing methods therefore

Life of this patent

Memory device with programmable self-refreshing and testing methods therefore

Life of this patent

Abstract

Claims20