Semiconductor memory device with precharge time improved

A semiconductor memory device, comprising:

• a memory cell array composed of a plurality of memory cells arranged in a matrix manner and at least one reference memory cell, wherein a plurality of digit lines are respectively connected to columns of memory cells, a plurality of word lines are respectively connected to rows of memory cells, and a reference digit line is connected to said reference memory cell;
• an address circuit for selecting one of said plurality of digit lines and one of said plurality of word lines in response to input of an address to select one of said plurality of memory cells;
• a sense amplifier connected to said plurality of digit lines and said reference digit line, for sensing data which has been stored in said selected memory cell in response to a first control signal which is active during a read access cycle;
• a discharging circuit for discharging charge of at least one of said plurality of digit lines which is connected to the selected memory cell and charge of said reference digit line in response to a second control signal;
• and
• control means for outputting said first control signal to said sense amplifier in a chip enable signal and outputting said second control signal to said discharging circuit in response to the input of the address and said first control signal.

A method of reading a data in a semiconductor memory device, comprising the steps of:

• selecting one of a plurality of memory cells arranged in a matrix manner in accordance with an inputted address, wherein a plurality of digit lines are respectively connected to columns of memory cells, a plurality of word lines are respectively connected to rows of memory cells, and a reference digit line is connected to a reference memory cell;
• disconnecting said plurality of digit lines and said reference digit line from said ground potential in a first portion of said current read access cycle;
• connecting a selection digit line of said plurality of digit lines which is connected to the selected memory cell and said reference digit line to a sense amplifier in said first portion of said current read access cycle;
• in said first portion of said current read access cycle, charging said selection digit line in accordance with a data which has been stored in the selected memory cell, and charging said reference digit line in accordance with a reference data which has been stored in said reference memory cell;
• and
• sensing the data, which has been stored in the selected memory cell, from a potential of said selection digit line and a potential of said reference digit line by said sense amplifier in said first portion of said current read access cycle.