Sense amplifier driving circuit

Abstract

A sense amplifier driving circuit includes bit-line connection transistors connected to link bit lines on the side of memory cells with bit lines on the side of a sense amplifier, a circuit for controlling ON/OFF operations of the bit-line connection transistors, and first and second capacitors coupled to respective sources of nMOS transistors and pMOS transistors constituting the sense amplifier. After a word line linked to the memory cell is turned ON to output cell data to the bit lines, the potentials at input gates of the bit-line connection transistors are lowered to a level permitting narrowing-down of a current flowing in the bit lines. Moreover, after the sense amplifier is activated, a difference voltage between the bit lines on the side of the sense amplifier is amplified sufficiently, and then a data read operation is completed. Thereafter, the bit-line connection transistors are turned ON to overdrive the sense amplifier through the first and second capacitors. This constitution contributes to a realization of a sense amplifier that can operate with a low power consumption and at high speed even at a low supply voltage.

Dependencies are inferred from the claim text.