Test circuit

A test circuit comprising a shift register group for row address having first to nth row address registers and a shift register group for column address having first to mth column address registers (n and m are natural numbers of 2 or larger);

• and
• said first to nth row address registers and said first to mth column address registers storing different first and second logics constituting a first binary logic, as configuration data configuring address data,
• said test circuit testing a storage circuit having memory cells that are specified with row address data obtained by decoding said configuration data stored in said first to nth row address registers and column address data obtained by decoding said configuration data stored in said first to mth column address registers:
• wherein said nth to first row address registers and said mth to first column address registers are connected in series in this order,
• said nth row address register being supplied with said configuration data which is shifted in said nth to first row address registers and said mth to first column address registers in this order to provide all cycle sequence data as said address data,
• and wherein an input terminal of said storage circuit is supplied with test data,
• said test data selectively taking one of the different first and second logics which constitutes a second binary logic, depending on whether the number s (n.gtoreq.s.gtoreq.0) of said first logics of said first binary logic continuously stored from said first row address register toward said nth row address register is an even number or an odd number, in a first case where said first logic of said first binary logic is stored in said mth column address register, and
• said test data selectively taking one of the different first and second logics which constitutes a third binary logic, depending on whether the number t (n.gtoreq.t.gtoreq.0) of said second logics of said first binary logic continuously stored from said first row address register toward said nth row address register is an even number or an odd number, in a second case where said second logic of said first binary logic is stored in said mth column address register.