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US 5,703,815 AGranted
High-speed semiconductor memory system
AssigneeNEC Corporation
InventorsShigeru Kuhara, Hideo Toyoshima
Life of this patent
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AssigneeNEC Corporation
InventorsShigeru Kuhara, Hideo Toyoshima
Estimating the term…
A semiconductor memory system is provided in which a wave-pipeline operational frequency is enhanced by reducing the cycle time through a reduction in a difference in the signal delay time caused by differences of data path lengths. A delay circuit is inserted into a signal path having a smaller delay time between an address input section and data output section, thereby reducing a difference in the signal delay time caused by differences of data path lengths, which in turn reduces the cycle time to enhance the wave-pipeline operational frequency. Alternatively, an arrangement may be made to increase the signal delay time of a driver and/or sense amplifier for a smaller signal path length. In another aspect, a maximum differences in voltage drops between memory cells is reduced by controlling the resistance of a charge section for a bit line.
A semiconductor system comprising an input flip-flop for receiving input address signals in sequence, an address decoder for decoding each of said input address signals to generate a selection signal, a memory cell array having a plurality of memory cells arranged in an array, one of said memory cells being selected by said selection signal, a read-out section for reading out data from selected one of said memory cells to generate a data signal, an output flip-flop for outputting said data signal outside said memory system, each of said input flip-flop, address decoder, memory cell array, read-out section and output flip-flop defining a plurality of signal paths for respective signal components of a corresponding one of said signals, said plurality of signal paths including a first signal path and a second signal path which has a path length larger than a path length of said first signal path, at least one of said address decoder and read-out section has a first driver for driving said first signal path and a second driver for driving said second signal path, said first driver has a first current drivability larger than a second current drivability of said second driver.
A semiconductor system comprising an input flip-flop for receiving input address signals in sequence, an address decoder for decoding each of said input address signals to generate a selection signal, a memory cell array having a plurality of memory cells arranged in an array, a plurality of pairs of bit lines extending in a column direction, a plurality of word lines extending in a row direction, each of said pair of bit lines and each of said plurality of word lines being responsive to corresponding selection signal for selecting one of said memory cells, a read-out section for reading out data from selected one of said memory cells to generate a data signal, an output flip-flop for outputting said data signal outside said memory system, a pair of charge section, each having a variable resistance responsive to said selection signal to thereby reduce the difference between voltage drops of said memory cells connected in one of said pairs of bit lines.
Dependencies are inferred from the claim text.