Semiconductor memory device having dual boosting circuits to reduce energy required to supply boosting voltages

A semiconductor memory device comprising a boost circuit that produces boosted voltages from a power supply voltage, said boosted voltages having different voltage values,

• wherein said boost circuit includes a plurality of boost circuits,
• wherein the plurality of boost circuits includes a first boost circuit that produces a first boosted voltage to be supplied to word lines for selecting memory cells and circuits which connect bit lines serving as data transfer paths to sense amplifiers, and a second boost circuit that produces a second boosted voltage to be supplied to a circuit which precharges the bit lines,
• wherein the second boosted voltage is lower than the first boosted voltage,
• wherein the first boost circuit includes:
• a first switch element having a first end supplied to the power supply voltage, and a second end;
• a second switch element having a first end connected to the second end of the first switch element, and a second end;
• a third switch element having a first end connected to the second end of the second switch element, and a second end via which the first boosted voltage is output;
• a first capacitor having a first end connected between the first and second switch elements, and a second end supplied with a first driving signal;
• and
• a second capacitor having a first end connected between the second and third switch elements, and a second end supplied with a second driving signal which corresponds to an inverted version of the first driving signal, and
• wherein said second boost circuit includes:
• a fourth switch element having a first end supplied with the power supply voltage, and a second end;
• a fifth switch element having a first end connected to the second end of the fourth switch element, and a second end via which the second boosted voltage is output;
• and
• a third capacitor having a first end connected between the fourth and fifth switch elements, and a second end supplied with a third driving signal.

A semiconductor memory device comprising:

• pairs of bit lines;
• word lines;
• first circuits which are respectively coupled to the pairs of the bit lines and precharge the pairs of bit lines in accordance with a first control signal;
• sense amplifiers respectively coupled to the pair of bit lines;
• a second circuit which selectively drives the word lines by a second control signal;
• and
• a third circuit which produces first and second boosted voltages from a power supply voltage and supplies the first and second boosted voltages to the first and second circuits, respectively, wherein the first control signal is produced from the first boosted voltage and the second control signal is produced from the second boosted voltage,
• wherein the first boosted voltage is lower than the second boosted voltage.