Multi-bit data output buffer for semiconductor memory device

Abstract

A multi-bit data output buffer for a semiconductor memory device, comprising a data input circuit for inputting at least two bit data, at least two bit data buffering circuits, each of at least two bit data buffering circuits buffering a corresponding one of at least two bit data from the data input circuit, and a bit data comparison circuit for controlling the amounts of current flowing to at least two bit data buffering circuits according to logic values of at least two bit data from the data input circuit. According to the present invention, the multi-bit data output buffer is capable of minimizing the generation of noise in the output data and enhancing a response speed of the output data with respect to the input data.

Dependencies are inferred from the claim text.