Data output buffer circuit of semiconductor memory device
AssigneeSamsung Electronocs Co., Ltd.
InventorsSeung-Moon Yoo, Jei-Hwon Yoo
Life of this patent
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Abstract
A voltage detection unit between a data output buffer terminal and the gate a transistor which is used to dissipate a high level voltage on the internal data line. The detection unit thus prevents an undesired electrical path from existing in the data output buffer circuit. In one embodiment, the detection unit consists of an NMOS and PMOS transistor connected in series and having a shared node connected to the voltage dissipating transistor. In another embodiment, there is also connected an invertor between the shared node and the gates of the NMOS and PMOS transistors.
Claims23
A data output buffer circuit of a semiconductor memory device which shares data input/output lines with other semiconductor memory devices, said circuit comprising:
- a first input node which receives an output data signal;
- a second input node which receives an inverted output data signal;
- an output node for outputting a buffer output data signal having an output voltage, said buffer output data signal derived from said output data signal and said inverted output data signal;
- a pull-up circuit connected between a first voltage and said output node, said pull-up circuit being controlled by said output data signal;
- a pull-down circuit connected between said output node and a second voltage, said pull-down circuit being controlled by said inverted output data signal;
- a voltage detection circuit connected between said first voltage and said output node, said voltage detection circuit inputting said buffer output data signal, detecting an output voltage level of said output voltage, and producing a detected voltage signal;
- and
- a switch circuit connected between said first input node and said second voltage, said switch circuit including a switch input which receives said detected voltage signal.
A data output buffer circuit of a semiconductor memory device which shares data input/output lines with other semiconductor memory devices, said circuit comprising:
- a first input node which receives an output data signal;
- a second input node which receives an inverted output data signal;
- an output node for outputting a buffer output data signal having an output voltage, said buffer output data signal derived from said output data signal and said inverted output data signal;
- a pull-up circuit connected between a first voltage and said output node, said pull-up circuit being controlled by said output data signal;
- a pull-down circuit connected between said output node and a second voltage, said pull-down circuit being controlled by said inverted output data signal;
- a first switch circuit connected between said first input node and said output node, said first switch circuit being controlled by a third voltage;
- a voltage detection circuit connected between said first voltage and said output node, said voltage detection circuit inputting said buffer output data signal, detecting an output voltage level of said output voltage, and producing a detected voltage signal, said voltage detection circuit including:
- a first MOS transistor connected between said first voltage and a switch input, said first MOS transistor including a first gate electrode;
- a second MOS transistor connected between said switch input and said output node, said second MOS transistor including a second gate electrode;
- and
- an inverter having a control input and a control output, said control output connected to said first and second gate electrodes, said inverter generating a control output signal at said control output, said control output signal having a control output voltage level that controls said first and second MOS transistors and which is dependent on a trip point that sets a predetermined voltage that will cause a change in logic state of said control output signal;
- and
- a second switch circuit connected between said first input node and said second voltage, said second switch circuit being connected to said switch input and to said control input of said voltage detector circuit.
A data output buffer circuit of a semiconductor memory device which shares data input/output lines with other semiconductor memory devices, said circuit comprising:
- a first input node which receives an output data signal;
- a second input node which receives an inverted output data signal;
- an output node for outputting a buffer output data signal having an output voltage, said buffer output data signal derived from said output data signal and said inverted output data signal;
- a pull-up circuit connected between a first voltage and said output node, said pull-up circuit being controlled by said output data signal;
- a pull-down circuit connected between said output node and a second voltage, said pull-down circuit being controlled by said inverted output data signal;
- a first switch circuit connected between said first input node and said output node, said first switch circuit being controlled by a third voltage;
- a voltage detection circuit connected between said first voltage and said output node, said voltage detection circuit inputting said buffer output data signal, detecting an output voltage level of said output voltage, and producing a detected voltage signal, said voltage detection circuit including:
- a first MOS transistor connected between said first voltage and a switch input, said first MOS transistor including a first gate electrode connected to said third voltage;
- and
- a second MOS transistor connected between said switch input and said output node, said second MOS transistor including a second gate electrode connected to said third voltage;
- and
- a second switch circuit connected between said first input node and said second voltage, said second switch circuit being connected to said switch input of said voltage detection circuit.
Dependencies are inferred from the claim text.