US 5,703,810 A · DRAM for texture mapping

Abstract

A latch/mask mechanism that is located between the sense amplifiers of a DRAM and the data bus. The latch/mask mechanism decouples the data bus from the sense amplifiers and permits innovative, time saving functionality during read and write operations. During a write operation, the latch can receive only those byte(s) or a row of bytes to be written. Corresponding mask bits are set to indicate those bytes to be written. Logic in the device transfers only those bytes in the row to be written to the sense amplifiers for writing to memory, leaving the data of remaining bytes in memory intact. Read operations are rendered more efficient by enabling logic, coupled to column select logic, to automatically transfer from the latch the byte selected by the column select logic and the adjacent byte. This time saving feature is particularly useful for computer graphics applications which utilize linear interpolation processes.

Claims13

Dependent claims

A dynamic random access memory (DRAM) comprising:

a plurality of memory cells organized into a memory array;
a plurality of sense amplifiers, each one of the sense amplifiers coupled to a memory cell of the plurality of memory cells such that data transferred to the sense amplifiers is written to the coupled memory cells during a write operation;
a latch/mask device comprising a plurality of latches to store data bits arranged in bytes and mask bits, one mask bit for byte of data, each one of the plurality of latches coupled to one sense amplifier of the plurality of sense amplifiers, the state of each mask bit controlling whether the corresponding byte is to be transferred to the array such that at least one selected byte of the bytes of latches is transferred to the sense amplifiers for transfer to coupled memory cells without affecting the state of memory cells coupled to sense amplifiers coupled to non-selected bytes of the bytes of latches.

A dynamic random access memory (DRAM) comprising:

a plurality of memory cells storing data bits organized into bytes, wherein a row of the memory array is composed of a plurality of bytes, each byte identified by an address;
a plurality of sense amplifiers, each one of the sense amplifiers coupled to a memory cell of the plurality of memory cells such that a row of data bits that includes a byte of data bits identified by a first address specified by a first read operation are transferred from the memory cells to the sense amplifiers during the first read operation;
a latch device comprising a plurality of latches to store data bits arranged in bytes each one of the plurality of latches coupled to one sense amplifier of the plurality of sense amplifiers, such that a row of data bits are transferred from the sense amplifiers to the latch device during the first read operation;
a data bus configured to transfer data bits from the latch device during the first read operation;
and
logic in the DRAM to control the latch device to transfer the byte identified by the first address and an adjacent byte during the first read operation from the latch device to the data bus.

3 more elements

Dependencies are inferred from the claim text.

DRAM for texture mapping

Life of this patent

DRAM for texture mapping

Life of this patent

Abstract

Claims13