EEPROM with enhanced reliability by selectable V.sub.PP for write and erase

A method for generating an erasure voltage and a programming voltage for an EEPROM array having a plurality of cells, the cells of the EEPROM array being capable of erasure and programming, comprising the steps of:

• generating a signal having an increasing voltage;
• monitoring said signal and terminating the increase in voltage of said signal when said signal reaches a first selected maximum level in an erase operation of at least one cell of said EEPROM array;
• and
• monitoring said signal and terminating the increase in voltage of said signal when said signal reaches a second selected maximum level in a program operation of at least one cell of said EEPROM array.

A voltage regulator for generating an erasure voltage and a programming voltage for an EEPROM array having a plurality of cells, the cells of the EEPROM array being capable of erasure and programming, comprising:

• a voltage generator that generates a voltage V.sub.PP having a waveform characteristic of increasing level over time, and being provided to the EEPROM array for erasure and programming of the cells thereof;
• first means, coupled to said voltage generator, for monitoring V.sub.PP during an erasure operation of at least one cell in the EEPROM array and for terminating the increase in level of V.sub.PP when V.sub.PP reaches a first predetermined voltage level selected for a desired erasure characteristic of said EEPROM array;
• and
• second means, coupled to said voltage generator, for monitoring V.sub.PP during a programming operation of at least one cell in the EEPROM array and for terminating the increase in level of V.sub.PP when V.sub.PP reaches a second predetermined voltage level selected for a desired programming characteristic of said EEPROM array.

A voltage generator for generating an erasure voltage and a programming voltage for an EEPROM array having a plurality of cells, the EEPROM array being capable of erasure and programming, comprising:

• a clock generator capable of generating a clock signal;
• a voltage multiplier coupled to said clock generator that provides a voltage V.sub.PP that increases in level in response to said clock signal, and being provided to the EEPROM array for erasure and programming of the cells thereof;
• first means coupled to said voltage multiplier for monitoring V.sub.PP and for disabling said clock generator when V.sub.PP reaches a first predetermined voltage level selected for a desired erasure characteristic of said EEPROM array;
• and
• second means coupled to said voltage multiplier for monitoring V.sub.PP and for disabling said clock generator when V.sub.PP reaches a second predetermined voltage level selected for a desired programming characteristic of said EEPROM array.

A voltage generator for generating an erasure voltage and a programming voltage for an EEPROM array having a plurality of cells, the EEPROM array being provided with a first, supply voltage V.sub.DD that is less than the required levels for erasure and programming of the cells of the array, comprising:

• a clock generator capable of generating a clock signal;
• a voltage multiplier, coupled to said clock generator, responsive to V.sub.DD, that provides a second, output voltage V.sub.PP that increases in level in response to said clock signal;
• first means, coupled to said voltage multiplier, for monitoring V.sub.PP and for providing a third voltage scaled by a first amount with respect to V.sub.PP ;
• a first comparator, coupled to said first means, for comparing said third voltage to a fourth, reference voltage and for providing an output signal when said third voltage exceeds said fourth voltage;
• second means, coupled to said voltage multiplier, for monitoring V.sub.PP and for providing a fifth voltage scaled by a second amount with respect to V.sub.PP ;
• a second comparator, coupled to said second means, for comparing said fifth voltage to said fourth voltage and for providing an output signal when said fifth voltage exceeds said fourth voltage;
• and means, coupled to said clock generator, to said first comparator and to said second comparator, for disabling said clock generator
• in response to said output signal from said first comparator, during an erase operation of said EEPROM array, and
• in response to said output signal from said second comparator, during a programming operation of said EEPROM array.