Dynamically controlled, cross-stacked CAM cell

An apparatus that stores a bit in a content addressable memory, comprising:

• a storage cell comprising:
• a second node that stores an inverse of an address bit;
• a third node that stores the address bit;
• a read/write input that enables the address bit and the inverse of the address bit to be stored in the storage cell;
• a comparison circuit coupled to the storage cell through the second and third nodes, comprising:
• a first transistor of a first type having a source coupled to a source voltage node and a gate coupled to the second node;
• a second transistor of the first type having a source coupled to a drain of the first transistor, a gate coupled to a first input that carries a virtual address bit, and a drain coupled to a first node;
• a third transistor of the first type having a source coupled to the source voltage node and a gate coupled to the third node;
• a fourth transistor of the first type having a source coupled to a drain of the third transistor, a gate coupled to a second input that carries an inverse of the virtual address bit, and a drain coupled to the first node;
• a match indication line coupled to the first node that indicates a miss when values on the first and second inputs do not match values stored in the storage cell.