Method and apparatus for automatically designing logic circuit, and multiplier

A method of automatically designing a logic circuit for generating a multiplier M which receives an n-bit number X and an m-bit constant A as its inputs and outputs their product P, comprising the steps of:

• (a) calculating a constant A7 defined as A7=A=2.sup.K with respect to a bit position K (0.ltoreq.K.ltoreq.m-1) having the value of 1 in said constant A;
• (b) generating a multiplier M7 which receives said A7 and X as its inputs and outputs the product P7 of said A7 and X;
• and
• (c) generating a circuit which receives said X and P7 as its inputs and outputs the sum of said P7 and the product of said X and 2.sup.K, wherein
• said steps (a) to (c) are executed so as to generate said multiplier M.

A method of automatically designing a logic circuit for generating a multiplier M which receives an n-bit number X and an m-bit constant A as its inputs and outputs their product P, comprising the steps of:

• (a) if an integer K is 0<K<m-1, generating a multiplier M5 which receives a constant A5 composed of the low-order (K-1) bits of said constant A and said X as its inputs and outputs their produce P5;
• (b) generating a multiplier M6 which receives a constant A6 composed of the high-order (m-K) bits of said constant A and said X as its inputs and outputs their product P6;
• (c) if the K-th bit from the least significant bit in said constant A has the value of 1, generating a circuit which receives said X, P5, and P6 as its inputs and outputs the sum of the product of said X and 2.sup.K-1, the product of said P6 and 2.sup.K, and said P5;
• and
• (d) if the K-th bit from the least significant bit in said constant A has the value of 0, generating a circuit which receives said P5 and P6 as its inputs and outputs the sum of said P5 and the product of said P6 and 2.sup.K, wherein
• said steps (a) to (d) are executed so as to generate said multiplier M.

A method of automatically designing a logic circuit for generating a multiplier M which receives an n-bit number X and m-bit constant A as its inputs and outputs their product P, comprising the steps of:

• (a) generating a circuit which receives said constant A and number X as its inputs and outputs the product P0 of the one's complement A0 of said constant A and said X;
• (b) generating a circuit which receives said X as input and outputs the sum Q4 of the two's complement of said X and the product of said X and 2.sup.m ;
• and
• (c) generating a circuit which receives said P0 and Q4 as its inputs and outputs the sum of the two's complement Q0 of said P0 and said Q4;
• wherein
• said steps (a) to (c) are executed so as to generate said multiplier M.

A method of automatically designing a logic circuit for generating a multiplier M which receives an n-bit number X and an m-bit constant A as its inputs and outputs their product P, the method comprising the step of:

• depending on said constant A, selectively executing operation S or T to generate said multiplier M,
• wherein said operation S comprises the steps of:
• (a) if an integer K is 0<K<m, generating a multiplier M1 which receives a constant A1 composed of the low-order k bits of said constant A and said n-bit number X as its inputs, and outputs the product P1 of said constant A1 and n-bit number X;
• (b) generating a multiplier M2 which receives a constant A2 composed of the high-order (m-k) bits of said constant A and said n-bit number X as its inputs, and outputs the product P2 of said constant A2 and n-bit number X;
• and
• (c) generating a circuit which receives said P1 and P2 as its input, and outputs the sum of said P1 and the product of said P2 and 2.sup.K, and
• said operation T comprises the steps of:
• (a) calculating a constant A7 defined as A7=A-2.sup.K with respect to a bit position K (0.ltoreq.K.ltoreq.m-1) having the value of 1 in said constant A;
• (b) generating a multiplier M7 which receives said constant A7 and n-bit number X as its inputs and outputs the product P7 of said constant A7 and n-bit number X;
• and
• (c) generating a circuit which receives said n-bit number X and product P7 as its inputs, and outputs the sum of said product P7 and the product of said n-bit number X and 2.sup.K.

A method of automatically designing a logic circuit for generating a multiplier M which receives an n-bit number X and an m-bit constant A as its inputs, and outputs their product P, the method comprising the steps of:

• depending on said constant A, selectively executing operation S, T or U to generate said multiplier M,
• wherein said operation S comprises the steps of:
• (a) if an integer K is 0<K<m, generating a multiplier M1 which receives a constant A1 composed of the low-order k bits of said constant A and said n-bit number X as its inputs, and outputs the product P1 of said A1 and n-bit number X;
• (b) generating a multiplier M2 which receives a constant A2 composed of the high-order (m-k) bits of said constant A and said n-bit number X as its inputs, and outputs the product P2 of said A2 and n-bit number X;
• and
• (c) generating a circuit which receives said product P1 and product P2 as its input, and outputs the sum of said product P1 and the product of said product P2 and 2.sup.K,
• said operation T comprises the steps of:
• (a) calculating a constant A7 defined as A7=A-2.sup.K with respect to a bit position K (0.ltoreq.K.ltoreq.m-1) having the value of 1 in said constant A;
• (b) generating a multiplier M7 which receives said constant A7 and n-bit number X as its inputs, and outputs the product P7 of said constant A7 and X;
• and
• (c) generating a circuit which receives said n-bit number X and product P7 as its inputs, and outputs the sum of said P7 and the product of said n-bit number X and 2.sup.K, and
• said operation U comprises the steps of:
• (a) generating a circuit which receives said constant A and n-bit number X as its inputs and outputs the product P0 of the one's complement A0 of said constant A and said n-bit number X;
• (b) generating a circuit which receives said n-bit number X as its input, and outputs the sum Q4 of the two's complement of said X and the product of said X and 2.sup.m ;
• and
• (c) generating a circuit which receives said product P0 and sum Q4 as its inputs, and outputs the sum of the two's complement Q0 of said product P0 and said sum Q4.

An apparatus for automatically designing a logic circuit which generates a multiplier, said multiplier for providing a signal P composed of the product of a signal X, representing an n-bit number, and a signal A, representing an m-bit constant, comprising:

• an input means for inputting information on signals X, A, and P;
• a multiplier generating means for generating information on a multiplier M1, said multiplier M1 for providing a signal P1 composed of the product of a signal A1, representing the low-order K bits of signal A, and signal X, and, if K is 0<K<m, for generating information on a multiplier M2 for providing a signal P2 composed of the product of a signal A2, representing the high-order (m-K) bits of signal A, and signal X;
• a calculating circuit generating means for generating information on a calculating circuit which receives a signal Q1, composed of the high-order n bits of signal P1, and signal P2 as its inputs, and outputs the sum of Q1 and P2 as the high-order (n+m-K) bits of signal P and the low-order K bits of signal P1 as the low-order K bits of signal P;
• an output means for outputting information on said multipliers M1 and M2 generated by said multiplier generating means, and information on said calculating circuit generated by said calculating circuit generating means;
• and
• a determining means for determining the value of said integer K, based on the number L1 of the bits having the value of 1 in said signal A1 and on the number L2 of the bits having the value of 1 in said signal A2.

An apparatus for automatically designing a logic circuit which generates a multiplier for providing a signal P representing the product of a signal X representing an n-bit number and a signal A representing an m-bit constant, comprising:

• an input means for inputting information on said signals X, A, and P;
• a determining means for determining the value of the K-th bit from the least significant bit in said signal A if an integer K is 0<K<m;
• a multiplier generating means for generating information on a multiplier M5 for providing a signal P5 representing the product of a signal A5 composed of the low-order (K-1) bits of said signal A and said signal X and on a multiplier M6 for providing a signal P6 representing the product of a signal A6 composed of the high-order (m-K) bits of said signal A and said signal X;
• a first calculating circuit generating means for generating information on a first calculating circuit which receives said signals X, P5, and P6 as its inputs and outputs, as said signal P, the sum of the product of said signal X and 2.sup.K-1, the product of said signal P6 and 2.sup.K, and said signal P5, if the value of said K-th bit is determined to be 1 by said determining means;
• a second calculating circuit generating means for generating information on a second calculating circuit which receives said signals P5 and P6 as its inputs and outputs, as said signal P, the sum of said signal P5 and the product of said signal P6 and 2.sup.K, if the value of said K-th bit is 0;
• and
• an output means for outputting information on said multipliers M5 and M6 which were generated by said multiplier generating means and on said first and second calculating circuits which were generated by said first and second calculating circuit generating means, respectively.

An apparatus for automatically designing a logic circuit which generates a multiplier for providing a signal P representing the product of a signal X representing an n-bit number and a signal A representing an m-bit constant, comprising

• an input means for inputting information on said signals X, A, and P;
• a signal generating means for generating information on a signal A7 which is obtained by turning the value of the K-th bit (0.ltoreq.K.ltoreq.m-1) from the least significant bit in said signal A from 1 to 0;
• a multiplier generating means for generating information on a multiplier M7 for providing a signal P7 representing the product of said signal A7 and signal X;
• calculating circuit generating means for generating information on a calculating circuit which receives said signals P7 and X as its inputs and outputs, as P, a signal representing the sum of said signal P7 and the product of said signal X and 2.sup.K ;
• and
• an output means for outputting information on said multiplier M7 which was generated by said multiplier generating means and on said calculating circuit which was generated by said calculating circuit generating means.

An apparatus for automatically designing a logic circuit which generates an multiplier for providing a signal P representing the product of a signal X representing an n-bit number and a signal A representing an m-bit constant, comprising:

• an input means for inputting information on said signals X, A, and P;
• a determining means for determining whether or not the number of the bits having the value of 1 in said signal A is larger than a specified integer K (0<K<m);
• a logic NOT generating means for providing the logic NOT signal A0 of said signal A, depending on the result of determination by said determining means;
• a multiplier generating means for generating information on a multiplier M0 which receives said A0 and X as its inputs and provides a signal P0 representing the product of said A0 and X;
• a calculating circuit generating means for generating information on a calculating circuit which receives said X and an output signal P0 from said multiplier MO as its inputs and outputs, as said signal P, a signal representing the difference between the product of said X and (2.sup.m -1), and said P0;
• and
• an output means for outputting information on said multiplier M0 which was generated by said multiplier generating means and on said calculating circuit which was generated by said calculating circuit generating means.

An apparatus for automatically designing a logic circuit which generates a multiplier for providing a signal P representing the product of a signal X representing an n-bit number and a signal A representing an m-bit constant, comprising:

• an input means for inputting information on signals X, A, and P;
• a first determining means for determining whether or not the number of the bits having the value of 1 in said signal A is larger than a specified integer K (0<K<m);
• a second-determining means for determining whether or not the value of the most significant bit in said signal A is 1;
• a logic NOT means for providing the logic NOT signal A0 of said signal A, depending on the result of determination by said first determining means;
• a first multiplier generating means for generating information on a multiplier M0 which receives said A0 and X as its inputs and provides a signal P0 representing the product of said A0 and X:
• a first calculating circuit generating means for generating information on a first calculating circuit which receives said X and an output signal P0 from said multiplier M0 as its inputs and outputs, as said signal P, a signal representing the difference between the produce of said X and (2.sup.m -1), and said P0;
• a second multiplier generating means for generating information on a multiplier M1 for providing a signal P1 representing the product of a signal A1 composed of the low-order K bits of said signal A and said signal X and on a multiplier M2 for providing a signal P2 representing the product of a signal A2 composed of the high-order (m-K) bits of said signal A and said signal X, if an integer K is 0<K<m;
• a second calculating circuit generating means for generating information on a second calculating circuit which receives a signal Q1 composed of the high-order n bits of said signal P1 and said signal P2 as its inputs and outputs a signal representing the sum of Q1 and P2 as the high-order (n+m-K) bits of said signal P and outputs a signal composed of the low-order K bits of said signal P1 as the low-order K bits of said signal P;
• a third multiplier generating means for generating information on a multiplier M3 for providing a signal P3 representing the product of a signal A3 composed of the low-order (m-1) bits of said signal A and said signal X;
• a third calculating circuit generating means for generating information on a third calculating circuit which outputs said signal P3 as the low-order (m-1) bits of said signal P and which receives the signal Q1 composed of the high-order n bits of said signal P3 and said signal X as its inputs and outputs a signal representing the sum of said signal Q1 and said signal X as the high-order (n+1) bits of said signal P, if the value of said most significant bit is determined to be 1 by said second determining means;
• a fourth calculating circuit generating means for generating information on a fourth calculating circuit which outputs said signal P3 as the low-order (n+m-1) bits of said signal P and outputs a signal having the value of 0 as the high-order 1 bit of said signal P, if the value of said most significant bit is determined to be 0 by said second determining means;
• and
• an output means for outputting information on said multipliers M0, M1 and M2, and M3 which were generated by said first, second, and third multiplier generating means, respectively, and on said first, second, third, and fourth calculating circuits which were generated by said first, second, third, and fourth calculating circuit generating means, respectively.