US 5,703,800 A · Signal processor

Abstract

An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell is specified by a denotation of E(column number),y(row number)! where the column number x is 1.ltoreq.x.ltoreq.4 and the row number y is x.ltoreq.y.ltoreq.4. Each arithmetic cell has a multiplier and an adder for multiply-add operation. An arithmetic cell, specified by Ex,y! where 2.ltoreq.x.ltoreq.4 and x.ltoreq.y.ltoreq.4, receives data from an Ex-1,y! arithmetic cell via a direct bus as well as from an Ex-1,y-1! arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.

Claims20

Dependent claims

A signal processor comprising:

an arithmetic unit for performing arithmetic operations on data;
a first interface for receiving external data signals and for transmitting data corresponding to said received signals to said arithmetic unit;
and
a second interface for receiving data processed by said arithmetic unit and for providing data signals corresponding to said received data;
said arithmetic unit including an array of a plurality of concurrently operable arithmetic cells arranged in columns and rows wherein each of said arithmetic cells is specified by a denotation of Ex,y! where x is a column number subscript satisfying 1.ltoreq.x.ltoreq.M and y is a row number subscript satisfying x.ltoreq.y.ltoreq.M, M being a integer such that M.gtoreq.2, wherein:
an arithmetic cell, specified by E1,y! where 1.ltoreq.y.ltoreq.M, receives data from said first interface;
an arithmetic cell, specified by Ex,y! where 2.ltoreq.x .ltoreq.M and x.ltoreq.y.ltoreq.M, receives data directly from an Ex-1,y! arithmetic cell as well as directly from an Ex-1,y-1! arithmetic cell;
and
an EM,M! arithmetic cell provides data to said second interface.

6 more elements

A signal processor comprising:

an arithmetic unit for performing arithmetic operations on data;
a first interface for receiving external data signals and for transmitting data corresponding to said received signals to said arithmetic unit;
and
a second interface for receiving data processed by said arithmetic unit and for providing data signals corresponding to said received data;
said arithmetic unit including;
an array of a plurality of concurrently operable arithmetic cells arranged in columns and rows wherein each of said arithmetic cells is specified by a denotation of Ex,y! where x is a column number subscript satisfying 1.ltoreq.x.ltoreq.M and y is a row number subscript satisfying x.ltoreq.y.ltoreq.M, M being an integer such that M.gtoreq.2;
and
a plurality of time division multiplex common buses each of which is specified by a denotation of Bk! where k is an integer such that 1.ltoreq.k.ltoreq.M-1, wherein a common bus Bk! provides a path connecting an arithmetic cell specified by Ek,y! where k.ltoreq.y.ltoreq.M and an arithmetic cell specified by Ek+1,y! where k+1.ltoreq.y.ltoreq.M;
wherein:
an arithmetic cell, specified by E1,y! where 1.ltoreq.y.ltoreq.M, receives data from said first interface;
an arithmetic cell, specified by Ek+1,y! where k+1.ltoreq.y.ltoreq.M, receives data directly from an arithmetic cell, specified by Ek,y! where k.ltoreq.y.ltoreq.M through said common bus Bk!;
and
an EM,M! arithmetic cell provides data to said second interface.

10 more elements

A signal processor comprising:

an arithmetic unit for performing arithmetic operations on data;
and
a first and second interfaces each for receiving external data signals and for transmitting data corresponding to said received signal to said arithmetic unit, and each for receiving data processed by said arithmetic unit and for providing data signals corresponding to said received data;
said arithmetic unit including:
an array of plurality of concurrently operable arithmetic cells arranged in columns and rows wherein each of said arithmetic cells is specified by denotation of Ex,y! where x is a column number subscript satisfying 1.ltoreq.x.ltoreq.M and y is a row number subscript satisfying 1.ltoreq.y.ltoreq.M+1, M being an integer such that M.gtoreq.2;
and
a plurality of time division multiplex common buses each of which is specified by a denotation of Bk! where k is an integer such that 1.ltoreq.k.ltoreq.M-1, wherein a common bus bk! provides a path connecting an arithmetic cell specified by Ek,y! where 1.ltoreq.y.ltoreq.M+1 and an arithmetic cell specified by Ek+1,y! where 1.ltoreq.y.ltoreq.M+1;
wherein:
an arithmetic cell, specified by E1,y! where 2.ltoreq.y.ltoreq.M +1, receives data from said first interface;
an arithmetic cell, specified by Ek+1,y! where k+2.ltoreq.y.ltoreq.M+1, receives data directly from an arithmetic cell, specified by Ek,y! where k+1.ltoreq.y.ltoreq.M+1 as well as directly from an arithmetic cell, specified by Ek+1,y! where 1.ltoreq.y.ltoreq.k+1, through said common bus Bk!;
an EM,M+1! arithmetic cell provides data to said second interface;
an arithmetic cell, specified by EM,y! where 1.ltoreq.y.ltoreq.M, receives data from said second interface;
an arithmetic cell, specified by Ek,y! where 1.ltoreq.y.ltoreq.k, receives data directly from an arithmetic cell Ek+1,y! where 1.ltoreq.y.ltoreq.k+1 as well as directly from an arithmetic cell Ek,y! where k+1.ltoreq.y.ltoreq.M+1, through said common bus Bk!;
and
an E1,1! arithmetic cell provides data to said first interface.

12 more elements

Dependencies are inferred from the claim text.

Signal processor

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Signal processor

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Abstract

Claims20