Test ready compiler for design for test synthesis

In a computer implemented synthesis system, a method of compiling an HDL specification having associated design rule and performance constraints, said method comprising the computer implemented steps of:

• compiling said HDL specification to produce a netlist description of a circuit design wherein said netlist comprises functional logic blocks and connections there between, said step of compiling further comprising the steps of:
• (i) replacing non-scan sequential cells with scannable sequential cells specially adapted to apply test vectors to combinational logic of said design, said scannable sequential cells being technology dependent;
• (ii) installing a loopback connection between an output and an input of each scannable sequential cell to simulate a scan chain link;
• and
• (iii) performing mapping optimization to modify results of said step of installing a loopback connection in an effort to satisfy said design rule and performance constraints;
• and
• storing said netlist description into a memory unit of a computer system, said netlist description including said scannable sequential cells and said loopback connection of each scannable sequential cell.

A computer implemented synthesis system, said system having a processor coupled to a memory unit wherein said processor is programmed to perform logic processing, said system further comprising:

• logic for receiving an HDL specification representing a design to be realized in circuit form and storing said HDL specification in said memory unit;
• logic for receiving constraints applicable to said design;
• compile logic for compiling said HDL specification to produce a netlist description of said design wherein said netlist comprises functional logic blocks and connections there between, said compile logic further comprising:
• (i) logic for replacing a genetic HDL specified or inferred sequential cell with scannable sequential cells specially adapted to apply test vectors to combinational logic of said design;
• and
• (ii) loopback logic for installing a loopback connection between an output and an input of each scannable sequential cell;
• and
• store logic for storing said netlist description into said memory unit, said netlist description including said scannable sequential cells and said loopback connection of each scannable sequential cell.

A computer implemented synthesis system, said system having a processor coupled to a memory unit wherein said processor is programmed to perform logic processing, said system further comprising:

• logic receiving an HDL specification representing a design to be realized in circuit form and storing said HDL specification in said memory unit;
• logic receiving constraints applicable to said design;
• compile logic compiling said HDL specification to produce a netlist description of said design wherein said nefiist comprises scannable sequential cells, functional logic blocks and connections there between, said compile logic further comprising:
• loopback logic installing a loopback connection between an output and an input of each scannable sequential cell to simulate a scan link of a scan chain for design for test implemented circuitry;
• and
• store logic storing said netlist description into said memory unit, said netlist description including scannable sequential cells and said loopback connection of each scannable sequential cell.

In a computer implemented synthesis system, a method comprising the computer implemented steps of:

• receiving an HDL specification representing a design and storing said HDL specification in a computer memory unit;
• receiving performance constraints applicable to said design;
• compiling said HDL specification with a compiler to produce a netlist description of said design optimized to said performance constraints wherein said netlist comprises functional logic blocks and connections there between including generic sequential eelIs and combinational logic, said step of compiling further comprising the step of:
• replacing said generic cells of said HDL specification with scannable sequential cells specially adapted to apply test vectors to combinational logic of said design;
• storing said netlist description into said computer memory unit, said netlist description including said scarunable sequential cells;
• and
• identifying and marking as violated those scannable sequential cells that cannot be part of a valid scan chain and replacing said violated scannable sequential cells with non-scan sequential cells.