Multichip semiconductor structures with interchip electrostatic discharge protection, and fabrication methods therefore

A multichip semiconductor stack comprising:

• a first semiconductor device chip having a first substrate, a first Vcc supply, a first Vss supply, and a first input/output connect, said first semiconductor device chip further including a first intrachip electrostatic discharge protection circuit electrically coupled between said first input/output connect and said first Vcc supply, and between said first input/output connect and said first Vss supply;
• a second semiconductor device chip having a second substrate, a second Vcc supply, a second Vss supply, and a second input/output connect, said second semiconductor device chip further including a second intrachip electrostatic discharge protection circuit electrically coupled between said second input/output connect and said second Vcc supply, and between said second input/output connect and said second Vss supply;
• and
• an interchip electrostatic discharge protection network interconnecting said first semiconductor device chip and said second semiconductor device chip such that
• said first Vcc supply is electrically coupled to said second Vcc supply,
• said first Vss supply is electrically coupled to said second Vss supply,
• said first Vcc supply is electrically coupled to said second Vss supply, and
• said first Vss supply is electrically coupled to said second Vcc supply.

A method for fabricating a semiconductor structure comprising:

• (a) forming a multichip stack by stacking together a first semiconductor device chip having a first planar main surface and a second semiconductor device chip having a second planar main surface such that said first planar main surface is parallel to said second planar main surface;
• (b) metallizing a first edge surface of said multichip stack such that a substrate of said first semiconductor device chip is electrically connected to a substrate of said second semiconductor device chip;
• and
• (c) subsequent to said step (b), forming a metallization pattern on a second edge surface of said semiconductor structure, said metallization pattern including at least one external connect of said first semiconductor device chip and at least one external connect of said second semiconductor device chip.