An apparatus for reducing and magnifying picture size of a video composite signal modulated with a color sub-carrier according to an NTSC system composed of sequences of data of an even and an odd frame, said even frame composed of a first field beginning at 0 phase of the color sub-carrier and a second field, and said odd frame composed of a first field beginning at .pi. phase of the color sub-carrier and a second field;
- comprising:
- a video composite signal source for delivering the video composite signal, the color sub-carrier, and vertical and horizontal synchronous signals of the video composite signal, said vertical and said horizontal synchronous signals being rectangular pulse signals at logic OFF for every respective vertical and horizontal blanking interval;
- a clock generator for generating a clock signal having a frequency of four times the frequency of, and synchronized with, the color sub-carrier;
- an A/D converter for sampling the video composite signal in synchronization with said clock signal, and converting the video composite signal into digital data composed of a sequence of pairs of data, each of said pairs of data being one of an even pair of data sampled at 0 phase and .pi./2 phase of the color sub-carrier and an odd pair of data sampled at .pi. phase and 3.pi./2 phase of the color sub-carrier;
- means for storing said digital data in each of a pair of line buffers alternately according to output logic of a first flip-flop driven by said horizontal synchronous signal, each of said pair of line buffers storing said digital data of a line sequentially in addresses indicated by a write line address counter which counts said clock signal when said horizontal synchronous signal is at logic ON and is reset by each rising edge of said horizontal synchronous signal, said write line address counter being reset to 0 when said digital data are data of the first field of the even frame or the second field of the odd frame, and is reset to 2 when said digital data are data of the second field of the even frame or the first field of the odd frame;
- means for reading out said digital data sequentially from addresses indicated by a read line address counter of each of said pair of line buffers alternately according to inverse logic of said first flip-flop, said read line address counter counting said clock signal when said horizontal synchronous signal is at logic ON and reset to 0 by each rising edge of said horizontal synchronous signal;
- means for writing said digital data read out from said pair of line buffers in each of a first field buffer and a second field buffer alternately in addresses indicated by a first x-address generator and a first y-address generator according to output logic of a second flip-flop driven by said vertical synchronous signal delayed by one period of said horizontal synchronous signal,
- said first x-address generator generating write x-addresses reset to an initial write x-address indicated by a control means by every rising edge of said horizontal synchronous signal wherein the least significant bit of each of said write x-addresses is output from an one stage binary counter counting said clock signal while said horizontal synchronous signal is at logic ON and the other higher bits of each of said write x-addresses are output from a counter counting output of a first variable frequency divider which frequency-divides said clock signal delivered while said horizontal signal is at logic ON by 2N, and
- said first y-address generator generating write y-addresses reset to an initial write y-address indicated by said control means by every rising edge of said vertical synchronous signal delayed and increasing in accordance with output of a second variable frequency divider which frequency-divides said horizontal synchronous signal delivered while said vertical synchronous signal delayed is at logic ON by N,
- where N is a positive integer indicated by said control means and is 1 when the picture size is not reduced and is n when the picture size is reduced to 1/n, n being a positive integer;
- means for generating a second vertical synchronous signal and a second horizontal synchronous signal for displaying a picture;
- means for generating first and second display data by reading out simultaneously said digital data stored in both of said first and said second field buffers respectively from same addresses indicated by a second x-address generator and a second y-address generator,
- said second x-address generator generating read x-addresses reset to an initial read x-address indicated by said control means by every rising edge of said second horizontal synchronous signal wherein the least significant bit of each of said read x-addresses is output from an one stage binary counter counting said clock signal while said second horizontal synchronous signal is at logic ON and the other higher bits of each of said read x-addresses are output from a counter counting output of a third variable frequency divider which frequency-divides said clock signal delivered while said second horizontal signal is at logic ON by 2M, and
- said second y-address counter generating read y-addresses reset to an initial read y-address indicated by said control means by every rising edge of said second vertical synchronous signal and increasing in accordance with output of a fourth variable frequency divider which frequency-divides said second horizontal synchronous signal delivered while said second vertical synchronous signal is at logic ON by M,
- where M is a positive integer indicated by said control means and is 1 when the picture size is not magnified and is m when the picture size is magnified by m, m being a positive integer;
- a first D/A converter and a second D/A converter for converting said first and said second display data to a first analog signal and a second analog signal respectively;
- a demodulator for demodulating said first and said second analog signals into a luminance component, an in-phase component and a quadrature component of color signals for displaying said picture, having,
- an analog adder for obtaining said luminance component by adding said first and said second analog signals,
- a first analog subtracter which subtracts said second analog signal from said first analog signal,
- a second analog subtracter which subtracts said first analog signal from said second analog signal,
- a selector which selects and outputs an output of said first analog subtracter when a control signal is at logic ON and an output of said second analog subtracter when said control signal is at logic OFF, said control signal being controlled at logic OFF when the picture size is reduced to 1/2n, n being a positive integer, by said control means,
- a fifth variable frequency divider and a sixth variable frequency divider, controlled by said control means, for generating said control signal when the picture size is reduced to 1/(2n+1), n being a positive integer not less than 0, and when the picture size is not reduced, said fifth variable frequency divider frequency-dividing said clock signal delivered while said second horizontal synchronous signal is at logic ON by 4.times.N, and said sixth variable frequency divider frequency-dividing said second horizontal synchronous signal delivered while said second vertical synchronous signal is at logic ON by 2.times.N, and said control signal being obtained from an output of said fifth variable frequency divider inverted while an output of said sixth variable frequency divider is at logic ON, where N is a positive integer indicated by said control means and is 1, when the picture size is reduced to 1/(2n+1), and is m when the picture size is magnified by m;
- a first sample hold sampling said output of said selector for holding and outputting said in-phase component according to output logic of a third flip-flop driven by said clock signal, and
- a second sample hold sampling said output of said selector for holding and outputting said quadrature component according to inverse logic of said third flip-flop;
- a matrix circuit for generating R, G and B signals from said luminance, said in-phase and said quadrature components;
- and
- a display supplied with said R, G and B signals and controlled by a sweep generator synchronized with said second vertical synchronous signal and said second horizontal synchronous signal.