Video signal compression apparatus for horizontal compression of a video signal

A video signal compression apparatus for compressing a video signal comprising:

• memory means for storing an input video signal and outputting data value D.sub.n for address A.sub.n and data value D.sub.n+1 for address A.sub.n+1 when a read address A.sub.n is given;
• value generator means for counting a number of system clock pulses and outputting a previously written count value corresponding to said number of counted system clock pulses;
• signal selector means for selecting one of the count value and a fixed value to generate a selector output value;
• register means for storing and outputting a register value;
• first adder means for adding the selector output value and the register value to generate an adder output value;
• said register means for latching the adder output value, wherein an integer part of the adder output value is said read address A.sub.n ;
• subtracter means for subtracting data D.sub.n from data D.sub.n+1 and generating a subtraction value;
• multiplier means for multiplying said subtraction value by a decimal part of the register value to generate a multiplier output value;
• and
• second adder means for adding the data value D.sub.n and the multiplier output value to generate said compressed video signal.