Signal driver circuit for liquid crystal displays

A signal driver circuit for driving an LCD panel, comprising:

• a plurality of data input lines, said plurality of data input lines comprising most significant data input lines and least significant data input lines;
• and
• a plurality of decoder cells connected to said plurality of data input lines, said decoder cells comprising:
• a plurality of most significant input transistors connected to said most significant data input lines,
• a plurality of least significant input transistors connected to said least significant data input lines, and
• reset circuitry,
• wherein at least two of said plurality of decoder cells share said plurality of most significant input transistors.

A signal driver circuit for driving an LCD panel, comprising:

• a plurality of data input lines, said plurality of data input lines comprising most significant data input lines and least significant data input lines;
• and
• a plurality of decoder cells connected to said plurality of data input lines, said decoder cells comprising:
• a plurality of most significant input transistors connected to said most significant data input lines,
• a plurality of least significant input transistors connected to said least significant data input lines, and
• a voltage level shifting circuit,
• wherein at least two of said plurality of decoder cells share said plurality of most significant input transistors.

A decoder cell within an LCD driver, comprising:

• a plurality of data input lines;
• a latch circuit connected to said data input lines;
• and
• a reset circuit connected to said latch circuit,
• wherein said latch circuit holds a decoded state of said decoder cell and said reset circuit resets said latch circuit, said latch circuit comprising a plurality of first transistors connected in series, the gates of said first transistors connected to said plurality of input lines.

A decoder cell within an LCD driver comprising:

• a plurality of data input lines;
• latch circuit connected to said data input lines;
• and
• reset circuit connected to said latch circuit,
• wherein said latch circuit holds a decoded state of said decoder cell and said reset circuit resets said latch circuit, said latch circuit comprising,
• a plurality of first transistors connected in series, the gates of said first transistors connected to said plurality of input lines,
• a plurality of second transistors, at least one of said second transistors connected in series with said first transistors and a gate of at least one of said second transistors connected to a node between said series of said first transistors and at least one of said second transistors, and
• a third transistor, a gate of said third transistor connected to said node.

A decoder cell within an LCD driver comprising:

• plurality of data input lines;
• a latch circuit connected to said data input lines;
• and
• a reset circuit connected to said latch circuit,
• wherein said latch circuit holds a decoded state of said decoder cell and said reset circuit resets said latch circuit, said latch circuit comprising,
• a plurality of first transistors connected in series, the gates of said first transistors connected to said plurality of input lines;
• and
• a plurality of second transistors, at least one of said second transistors connected in series with said first transistors and a gate of at least one of said second transistors connected to a node between said series of said first transistors and at least one of said second transistors,
• wherein said reset circuit comprising:
• a first reset transistor, the source and drain of said first reset transistor connected to the respective source and drain of one of said second transistors;
• and
• a second reset transistor connected in series with said first plurality of transistors and one of said second transistors.

A signal driver circuit for driving an LCD panel, comprising:

• a plurality of decoder cells each comprising,
• a plurality of data input lines;
• a latch circuit connected to said data input lines;
• and
• a reset circuit connected to said latch circuit,
• wherein said latch circuit holds a decoded state of said decoder cell and said reset circuit resets said latch circuit, said latch circuit comprising, a plurality of first transistors connected in series, the gates of said first transistors connected to said plurality of input lines,
• said plurality of first transistors comprising most significant bit transistors and least significant bit transistors,
• wherein at least two of said plurality of decoder cells share at least one most significant bit transistor.

A decoder circuit within an LCD signal driver circuit for selecting a decode state corresponding to a voltage to be applied to an output of said signal driver circuit, comprising:

• a plurality of generally parallel data bus lines carrying a digital number representing a desired output voltage of said signal driver circuit and extending through said decoder circuit to at least one adjacent decoder circuit, said data bus lines comprising most significant bit data bus lines and least significant bit data bus lines;
• a plurality of most significant bit transistors having gates connected to said most significant bit data bus lines, said most significant bit transistors connected to a plurality least significant bit transistors for decoding at least two decode states;
• and
• an active area which said gates cross to form an abutting strand of said most significant bit transistors, said active area connected to a plurality of least significant bit transistors.