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US 5,703,608 AGranted
Signal processing circuit
AssigneeRohm Co., Ltd.
InventorKaeko Kuga
Life of this patent
Estimating the term…
Abstract
A signal processor alternately outputs two input signals to a common output terminal every predetermined period to form a single serial signal. A capacitor for holding the input signal is provided on each input signal transmitting path. A buffer is provided at each of the preceding and succeeding stages of each capacitor. The turning on and off of these buffers is controlled by a single switch. The switch is controlled so that when one capacitor is supplied with the input signal, the other capacitor outputs a signal.
Claims7
A signal processor comprising:
- a first input terminal supplied with a first signal;
- a second input terminal supplied with a second signal;
- first and second input buffers connected to the first and second input terminals, respectively;
- a first capacitor connected to an output side of the first input buffer and to a reference potential point for holding the first signal;
- a second capacitor connected to an output side of the second input buffer and to the reference potential point for holding the second signal;
- a first output buffer connected to the first capacitor;
- a second output buffer connected to the second capacitor;
- an output terminal supplied with outputs of the first and second output buffers;
- a power source for activating the first and second input buffers and the first and second output buffers;
- and
- switch means which alternately repeats a first period during which the first input buffer and the second output buffer are connected to the power source and a second period during which the second input buffer and the first output buffer are connected to the power source.
8 more elements
A signal processor comprising:
- a first input terminal supplied with a first video signal of a first field;
- a second input terminal supplied with a second video signal of a second field;
- first and second input buffers connected to the first and second input terminals, respectively;
- a first capacitor connected to an output side of the first input buffer and to a reference potential point for holding the first signal;
- a second capacitor connected to an output side of the second input buffer and to the reference potential point for holding the second signal;
- a first output buffer connected to the first capacitor;
- a second output buffer connected to the second capacitor;
- an output terminal supplied with outputs of the first and second output buffers and supplying the outputs to a liquid crystal display device of a non-interlace type;
- a power source for activating the first and second input buffers and the first and second output buffers;
- and
- switch means for alternately connecting 1) the first input buffer and the second output buffer to the power source during a first period and 2) the second input buffer and the first output buffer to the power source during a second period, wherein changeover of said switch means is controlled by a pulse for each pixel of the display device.
8 more elements
Dependencies are inferred from the claim text.