Switched capacitor input sampling circuit and method for delta sigma modulator

A delta sigma modulator comprising in combination:

• (a) a switched capacitor feedback reference voltage sampling circuit receiving a reference feedback voltage and having first and second terminals coupled to first and second charge summing conductors;
• (b) an integrator including an amplifier having first and second inputs coupled to the first and second charge summing conductors, respectively, a first integrating capacitor coupled between the first charge summing conductor and a first output of the amplifier and a second integrating capacitor coupled between the second charge summing conductor and a second output of the amplifier;
• (c) a comparator circuit having at least one input coupled to one of the first and second outputs of the amplifier;
• (d) a clock generating circuit adapted to generate a plurality of clock signals in accordance with "1" or "0" output signal levels produced by the comparator;
• and
• (e) a switched capacitor input sampling circuit having first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to the first and second charge summing conductors, respectively, the switched capacitor input sampling circuit including
• i. a first switch coupled between the first input terminal and a first conductor, and a second switch coupled between the second input terminal and a second conductor,
• ii. a third switch coupled between the first conductor and a bias voltage conductor, and a fourth switch coupled between the second conductor and the bias voltage conductor,
• iii. a first sampling capacitor coupled between the first conductor and a third conductor, and a second sampling capacitor coupled between the second conductor and a fourth conductor,
• iv. a fifth switch coupled between the third and fourth conductors, and
• v. a sixth switch coupled between the third conductor and the first terminal, and a seventh switch coupled between the fourth conductor and the second terminal.

In a delta sigma modulator including a switched capacitor feedback reference voltage sampling circuit, an integrator including an amplifier and first and second integrating capacitors, a comparator, a clock generating circuit adapted to generate a plurality of clock signals in accordance with "1" or "0" output signal levels produced by the comparator, the improvement comprising in combination:

• a switched capacitor input sampling circuit having first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to the first and second integrating capacitors, respectively, the switched capacitor input sampling circuit including
• (a) a first switch coupled between the first input terminal and a first conductor, and a second switch coupled between the second input terminal and a second conductor;
• (b) a third switch coupled between the first conductor and a bias voltage conductor, and a fourth switch coupled between the second conductor and the bias voltage conductor;
• (c) a first sampling capacitor coupled between the first conductor and a third conductor, and a second sampling capacitor coupled between the second conductor and a fourth conductor;
• (d) a fifth switch coupled between the third and fourth conductors;
• and
• (e) a sixth switch coupled between the third conductor and the first terminal, and a seventh switch coupled between the fourth conductor and the second terminal,
• the plurality of clock signals opening the third, fourth, sixth and seventh switches and closing the first, second, and fifth switches to effectuate sampling the differential analog input voltage across a series connection of the first and second sampling capacitors during a first clock phase,
• the plurality of clock signals opening the first, second and fifth switches and closing the third, fourth, sixth and seventh switches to effectuate transfer of sampled charge between the first sampling capacitor and the first integrating capacitor and to effectuate transfer of sampled charge between the second sampling capacitor and the second integrating capacitor during a second clock phase.

In a delta sigma modulator including a switched capacitor feedback reference voltage sampling circuit, an integrator including an amplifier and first and second integrating capacitors, a comparator, a clock generating circuit adapted to generate a plurality of clock signals in accordance with "1" or "0" output signal levels produced by the comparator, the improvement comprising in combination:

• a switched capacitor input sampling circuit having first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to the first and second integrating capacitors, respectively, the switched capacitor input sampling circuit including
• (a) a first switch coupled between the first input terminal and a first conductor, and a second switch coupled between the second input terminal and a second conductor;
• (b) a third switch coupled between the first conductor and a bias voltage conductor, and a fourth switch coupled between the second conductor and the bias voltage conductor;
• (c) a first sampling capacitor coupled between the first conductor and a third conductor, and a second sampling capacitor coupled between the second conductor and a fourth conductor 12;
• (d) a fifth switch coupled between the third and fourth conductors;
• and
• (e) means coupled to the first and second conductors for establishing an input common mode bias point for the amplifier without precharging either of the first and second conductors to any predetermined reference voltage.