Apparatus and method for controlling the loop bandwidth of a phase locked loop

A method of operating a phase lock loop (PLL) that generates an output frequency signal responsive to a reference frequency signal, wherein the output frequency signal and the reference frequency signal are each characterized by frequency and phase, wherein the PLL is operative in a first loop bandwidth state to maintain the output frequency signal substantially at a frequency indicative of the reference frequency signal, and is operative in a second loop bandwidth state to converge the output frequency signal to the frequency indicative of the reference frequency signal, the method comprising the steps of:

• detecting a phase error indicative of the difference between the phase of the reference frequency signal and the phase of the output frequency signal;
• and
• identifying the phase error as either desirable or undesirable;
• when the phase error is identified as desirable:
• determining a rate of change of the phase error over a first predetermined time period to provide an indication of frequency error between the frequency of the reference frequency signal and the frequency of the output frequency signal;
• and
• controlling a transition between the first and second loop bandwidth states of the PLL responsive to the indication of the frequency error;
• and
• when the phase error is identified as undesirable, operating in the second loop bandwidth state.

A method of operating a radio frequency transceiver, comprising the steps of:

• generating, with a frequency synthesizer, a synthesized frequency signal responsive to a frequency setting and a reference frequency signal, the synthesized frequency signal and the reference frequency signal are each characterized by frequency and phase, a phase error is indicative of the difference between the phase of the reference frequency signal and the phase of the synthesized frequency signal;
• translating a frequency of a modulated signal responsive to the synthesized frequency signal;
• and
• operating a phase lock loop (PLL) within the frequency synthesizer, wherein the PLL is operative in a first loop bandwidth state to maintain the synthesized frequency signal substantially at a first frequency setting, and operative in a second loop bandwidth state to converge the synthesized frequency signal to a second frequency setting, the method controlling the loop bandwidth of the PLL comprising the steps of:
• identifying the phase error as either desirable or undesirable;
• when the phase error is identified as desirable:
• determining a rate of change of the phase error over a first predetermined time period to provide an indication of frequency error between the frequency of the reference frequency signal and the frequency of the synthesized frequency signal;
• and
• controlling a transition between the first and second loop bandwidth states of the PLL responsive to the indication of the frequency error;
• and
• when the phase error is identified as undesirable, operating in the second loop bandwidth state.

In a phase lock loop (PLL) that generates an output frequency signal responsive to a reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, a phase error is indicative of the difference between the phase of the reference frequency signal and the phase of the output frequency signal, the PLL operative in a first loop bandwidth state to maintain the output frequency signal substantially at a frequency indicative of the reference frequency signal, and operative in a second loop bandwidth state to converge the output frequency signal to the frequency indicative of the reference frequency signal, an apparatus for controlling the loop bandwidth of the PLL comprising:

• a phase error identifier operative to identify the phase error as either desirable or undesirable;
• a rate of change determiner operative to determine, when the phase error is identified as desirable, a rate of change of the phase error over a first predetermined time period to provide an indication of frequency error between the frequency of the reference frequency signal and the frequency of the output frequency signal;
• and
• a loop bandwidth adjuster operative to control, when the phase error is identified as desirable, a transition between the first and second loop bandwidth states of the PLL responsive to the indication of the frequency error, and operative to operate, when the phase error is identified as undesirable, the PLL in the second loop bandwidth state.

A phase lock loop (PLL) generates an output frequency signal responsive to a reference frequency signal, wherein the output frequency signal and the reference frequency signal are each characterized by frequency and phase, and wherein the PLL is operative in a first loop bandwidth state to maintain the output frequency signal substantially at a frequency indicative of the reference frequency signal, and is operative in a second loop bandwidth state to converge the output frequency signal to the frequency indicative of the reference frequency signal, the PLL comprising:

• a phase detector operative to detect a phase error, indicative of the difference between the phase of the reference frequency signal and the phase of the output frequency signal;
• a phase error identifier operative to identify the phase error as either desirable or undesirable;
• a rate of change determiner operative to determine, when the phase error is identified as desirable, a rate of change of the phase error over a first predetermined time period to provide an indication of frequency error between the frequency of the reference frequency signal and the frequency of the output frequency signal;
• and
• a loop bandwidth adjuster operative to control, when the phase error is identified as desirable, a transition between the first and second loop bandwidth states of the PLL responsive to the indication of the frequency error, and operative to operate, when the phase error is identified as undesirable, the PLL in the second loop bandwidth state.

A radio frequency transceiver comprising:

• a frequency synthesizer operative to generate a synthesized frequency signal responsive to a frequency setting and a reference frequency signal, the synthesized frequency signal and the reference frequency signal are each characterized by frequency and phase, a phase error is indicative of the difference between the phase of the reference frequency signal and the phase of the synthesized frequency signal;
• a frequency translator operative to translate a frequency of a modulated signal responsive to the synthesized frequency signal;
• and
• a phase lock loop (PLL) within the frequency synthesizer, wherein the PLL is operative in a first loop bandwidth state to maintain the synthesized frequency signal substantially at a first frequency setting, and operative in a second loop bandwidth state to converge the synthesized frequency signal to a second frequency setting, an apparatus for controlling the loop bandwidth of the PLL comprising:
• a phase error identifier operative to identify the phase error as either desirable or undesirable;
• a rate of change determiner operative to determine, when the phase error is identified as desirable, a rate of change of the phase error over a first predetermined time period to provide an indication of frequency error between the frequency of the reference frequency signal and the frequency of the output frequency signal;
• and
• a loop bandwidth adjuster operative to control, when the phase error is identified as desirable, a transition between the first and second loop bandwidth states of the PLL responsive to the indication of the frequency error, and operative to operate, when the phase error is identified as undesirable, the PLL in the second loop bandwidth state.